Verification Hierarchy View

The Verification Hierarchy View presents the UVM object instance tree. An UVM object instance is a class member of an UVM based type that is created using an UVM factory create call.

To open the Verification Hierarchy view use the DVT: Focus on Verification View command. To populate the view, use the DVT: Select Verification Hierarchy Top command or the button in the view header.

For the selected UVM test, you have the option to view a statically elaborated hierarchy or perform a runtime elaboration in order to view testbench structures accurately reflecting the configuration at start of simulation.

../../_images/vscode_sv_select_top_webview.png

You can also position the editor cursor on the name of an UVM based class and use the command DVT: Show Verification Hierarchy. The Verification Hierarchy View opens with the chosen element set as the top of the hierarchy.

Scroll through the tree of instances using:

  • the mouse scroll wheel

  • the Arrow Up, Arrow Down, PgUp, PgDn keys

  • the vertical button bar on the right side of the tree

    • top-icon go to top of tree

    • up-icon up one page

    • page-up-icon up one element

    • page-down-icon down one element

    • down-icon down one page

    • bottom-icon go to bottom of tree

Double-click an instance to go to its UVM factory create call.

Right-click an instance to:

  • Show Diagram Generate the UVM Component Diagram of the selected instance. More details here.

  • Copy Hierarchy Path Copy the hierarchical path of the selected instance to clipboard.

  • Copy Copy the label text of the selected instance to clipboard.

../../_images/vscode_sv_right_click_verification_hierarchy_view.png

Double-click a port to go to its declaration.

Click an instance to see its ports in the lower panel. Right-click a port to copy its hierarchical path to clipboard (Copy Hierarchy Path ).

Right-click on a port and you have the options to copy its name and the full hierarchy path of the selected port.

You can use the filters to locate a specific instance or port. You may use slash ‘/’ characters to filter hierarchically one level and ‘//’ to filter hierarchically all the levels. You may use the dot ‘.’ character to filter instances that contain a specific port. See Quick Search in Views for more details.

For example, filtering hierarchically all the levels for a specific port name :

../../_images/vscode_sv_filter_verification_hierarchy_view.png

Setting Verification Hierarchy Top from the build configuration file

You can specify the top of the Verification Hierarchy by adding the +UVM_TESTNAME=<testname> directive to your build configuration file.

If +UVM_TESTNAME is specified multiple times, only the first occurrence is used.

The following directives can be used alongside +UVM_TESTNAME to configure UVM Runtime Elaboration:

  • +UVM_VERBOSITY=<verbosity> - Sets the UVM verbosity level.

  • +UVM_SEED=<seed> - Sets the random seed.

Note

If a top is already manually set in the Verification Hierarchy View, the +UVM_TESTNAME directive will not override it.

Note

The test specified by +UVM_TESTNAME will appear first in the list of tops, under the snapshots in the Select Verification Top menu.