Code Formatting

In order to format a selected region of code or an entire file, use the Format Selection or Format Document commands. All code formatting preferences are available at File > Preferences > Settings > Extensions > DVT > Text Editor > System Verilog > Formatting.

• Whitespace
• Indentation
• Vertical Alignment
  • Vertical Align Patterns (DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignPatterns)
• Line Wrapping
• Disable Format for Code Sections
• Preferences Keys