Module dram_001
Name |
Default |
Description |
---|---|---|
MEM_ADDR |
5 |
|
MEM_WIDTH |
16 |
Data width |
Name |
Type |
Direction |
Description |
---|---|---|---|
wr_clk |
wire logic |
input |
Write clock |
rd_clk |
wire logic |
input |
Read clock |
addr_wr |
wire logic [MEM_ADDR - 1 : 0] |
input |
Write address |
addr_rd |
wire logic [MEM_ADDR - 1 : 0] |
input |
Read address |
wr_en |
wire logic |
input |
Write enable |
data_wr |
wire logic [MEM_WIDTH - 1 : 0] |
input |
Write data |
data_rd |
reg [MEM_WIDTH - 1 : 0] |
output |
Read data (registered) |
Always Blocks
- always @ ( posedge wr_clk )
Memory Write
- always @ ( posedge rd_clk )
Memory Read
Instances
- ip_emac_top : ip_emac_top
- mac_top : ip_mac_top_g
- mac_rx_top : ip_mac_rx_top_g
- rx_data_dram : ip_mac_dram_002
dram_001 : dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(37))
- rx_dram_hash_0 : ip_mac_dram_004
dram_001 : dram_001 #(.MEM_ADDR(4), .MEM_WIDTH(32))
- rx_dram_hash_1 : ip_mac_dram_003
dram_001 : dram_001 #(.MEM_ADDR(4), .MEM_WIDTH(16))
- mac_tx_top : ip_mac_tx_top_g
- tx_data_dram : ip_mac_dram_001
dram_001 : dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(39))
×
Address width (9 -> 512 locations, 10->1024)