Module ip_mac_tx_dsplit_g
Block Diagram of ip_mac_tx_dsplit_g
Name |
Default |
Description |
|---|---|---|
MEM_ADDR |
6 |
Name |
Type |
Direction |
Description |
|---|---|---|---|
pi_reset |
wire logic |
input |
Global Software/Hardware Reset (transmit clock domain) |
pi_g_clock |
wire logic |
input |
Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, gated clock) |
pi_f_clock |
wire logic |
input |
Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, free clock) |
po_en_clock |
reg |
output |
Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable |
pi_data |
wire logic [31 : 0] |
input |
Signals comming in from the data FIFO related to data transfer FIFO Data bus (frame data 32-bit word) |
pi_sop |
wire logic |
input |
Start of data frame indication |
pi_eop |
wire logic |
input |
End of data frame indication |
pi_err |
wire logic |
input |
Error frame indication |
pi_pad |
wire logic |
input |
Pad append command, valid only when end of frame (When padding enable |
pi_crc |
wire logic |
input |
and frame has less than 64 bytes the CRC is appended regardless of the CRC append setting CRC append command, valid only when end of frame |
pi_byte |
wire logic [1 : 0] |
input |
Byte enable information |
pi_wr_addr |
wire logic [MEM_ADDR : 0] |
input |
Read & Write pointers TX FIFO write address information (used by tx state to determine the |
po_fc_addr |
reg [2 : 0] |
output |
FIFO condition full/empty/ready) Flow control read address |
pi_half_duplex |
wire logic |
input |
Half duplex flow control enable Half duplex operating mode |
po_rd_ptr |
wire logic [MEM_ADDR - 1 : 0] |
output |
Output Signals to buffer manager related to data transfer Memory read address |
po_rd_addr |
reg [MEM_ADDR : 0] |
output |
Used by TX FIFO to compute the memory state (full/empty/ready) |
po_fc_req |
reg |
output |
Request & Acknowledge Flow control frame transmit request |
po_data_req |
reg |
output |
Data frame transmit request |
pi_fc_ack |
wire logic |
input |
Flow control frame transmit acknowledge |
pi_data_ack |
wire logic |
input |
Data frame transmit acknowledge |
pi_fc_data |
wire logic [31 : 0] |
input |
Flow control generator interface Flow control frame data |
pi_fc_ready |
wire logic |
input |
New flow control frame ready |
pi_fc_tx_off |
wire logic |
input |
Flow control (pause frame was received, stop transmit command) |
pi_fc_sop |
wire logic |
input |
Flow control frame end |
pi_fc_eop |
wire logic |
input |
Flow control frame start |
pi_read |
wire logic |
input |
Read next data |
pi_remove |
wire logic |
input |
Remove current frame (drop frame) |
pi_reload |
wire logic |
input |
Reload current frame (retransmit) |
pi_update |
wire logic |
input |
Update read pointers (collision window out) |
pi_en_high |
wire logic |
input |
Enable High (MSB) |
po_data |
reg [7 : 0] |
output |
Signals comming in from the data FIFO related to data transfer Output 8-bit data |
po_sop |
reg |
output |
Start of data frame indication |
po_eop |
reg |
output |
End of data frame indication |
po_err |
reg |
output |
Error frame indication |
po_pad |
reg |
output |
Pad append command, valid only when end of frame (When padding enable |
po_crc |
reg |
output |
and frame has less than 64 bytes the CRC is appended regardless of the CRC append setting CRC append command, valid only when end of frame |
po_valid |
reg |
output |
Valid output data |
Always Blocks
- always @ ( read_ptr or pi_wr_addr )
Synchronous write, asynchronous read memory (FIFO output available)
- always @ ( posedge pi_g_clock or negedge pi_reset )
Split Data Counter
- always @ ( posedge pi_g_clock or negedge pi_reset )
Data Output Management
- always @ ( pi_fc_tx_off or pi_sop or prev_valid or pi_fc_ready or pi_fc_sop or unlock_sop )
Data or Flow Control Frame Request (Available)
- always @ ( posedge pi_g_clock or negedge pi_reset )
Delay And Unlock Signal Process
- always @ ( posedge pi_g_clock or negedge pi_reset )
# |
Current State |
Next State |
Condition |
Comment |
|---|---|---|---|---|
1 |
`DATA_DROP |
`FC_READ |
[(!(~ pi_reset) && (pi_fc_ack == 1'b1))] |
|
2 |
`DATA_DROP |
`SPLIT_WAIT |
[(!(~ pi_reset) && !(pi_fc_ack == 1'b1) && (reload_frame == 1'b1)), (!(~ pi_reset) && !(pi_fc_ack == 1'b1) && !(reload_frame == 1'b1) && (valid_data == 1'b1 && pi_sop == 1'b0 || unlock_sop == 1'b0))] |
|
3 |
`DATA_DROP |
`SPLIT_IDLE |
[(!(~ pi_reset) && !(pi_fc_ack == 1'b1) && !(reload_frame == 1'b1) && !(valid_data == 1'b1 && pi_sop == 1'b0 || unlock_sop == 1'b0) && (valid_data == 1'b1 && pi_sop == 1'b1 && unlock_sop == 1'b1))] |
|
4 |
`FC_READ |
`DATA_DROP |
[(!(~ pi_reset) && (remove_frame == 1'b1)), (!(~ pi_reset) && !(remove_frame == 1'b1) && (reload_frame == 1'b1)), (!(~ pi_reset) && !(remove_frame == 1'b1) && !(reload_frame == 1'b1) && (po_eop == 1'b1 && pi_read == 1'b1))] |
|
5 |
`SPLIT_WAIT |
`DATA_DROP |
[(!(~ pi_reset) && !(reload_frame == 1'b1))] |
|
6 |
`SPLIT_IDLE |
`SPLIT_WAIT |
[(!(~ pi_reset) && (reload_frame == 1'b1))] |
|
7 |
`SPLIT_IDLE |
`FC_READ |
[(!(~ pi_reset) && !(reload_frame == 1'b1) && (pi_fc_ack == 1'b1))] |
|
8 |
`SPLIT_IDLE |
`DATA_READ |
[(!(~ pi_reset) && !(reload_frame == 1'b1) && !(pi_fc_ack == 1'b1) && (pi_data_ack == 1'b1))] |
|
9 |
`DATA_READ |
`SPLIT_WAIT |
[(!(~ pi_reset) && (remove_frame == 1'b1)), (!(~ pi_reset) && !(remove_frame == 1'b1) && (reload_frame == 1'b1)), (!(~ pi_reset) && !(remove_frame == 1'b1) && !(reload_frame == 1'b1) && (po_eop == 1'b1 && valid_data == 1'b1 && pi_read == 1'b1)), (!(~ pi_reset) && !(remove_frame == 1'b1) && !(reload_frame == 1'b1) && !(po_eop == 1'b1 && valid_data == 1'b1 && pi_read == 1'b1) && !(split_cnt == 2'd0 && valid_data == 1'b1 && pi_read == 1'b1) && (po_eop == 1'b1 && valid_data == 1'b0 && pi_read == 1'b1))] |
- always @ ( posedge pi_f_clock or negedge pi_reset )
Data or Flow Control Frame Request (Available)
Instances
- ip_emac_top : ip_emac_top
- mac_top : ip_mac_top_g
- mac_tx_top : ip_mac_tx_top_g
tx_dsplit : ip_mac_tx_dsplit_g #(.MEM_ADDR(10))
Transmit memory address width (9 -> 512 locations, 10->1024)