Module ip_mac_mdio_g

ip_mac_mdio_g u_ip_mac_mdio_g ( .pi_reset(pi_reset), .pi_clock(pi_clock), .pi_master_mdio(pi_master_mdio), .po_master_mdio(po_master_mdio), .po_master_oni(po_master_oni), .po_mdio_err(po_mdio_err), .pi_mdio_wdata(pi_mdio_wdata), .po_mdio_rdata(po_mdio_rdata), .pi_mdio_start(pi_mdio_start), .po_mdio_done(po_mdio_done), .pi_mdio_rnw(pi_mdio_rnw), .pi_mdio_daddr(pi_mdio_daddr), .pi_mdio_raddr(pi_mdio_raddr) );

Block Diagram of ip_mac_mdio_g

The EMAC has a master management interface, which is used to access the PHY configuration registers. Depending on the configuration, the EMAC will either read the values from the PHY registers (auto-configuration mode) or set the values according to the programmed values (programming mode). The MDIO (po_master_mdio/pi_master_mdio) and MDC (po_master_mdc) ports are used to serially write and read management interface registers. A 2.5 MHz clock waveform must be provided to the MDC port on this interface.

Every management read/write instruction frame contains the following fields:

• PRE, Preamble - The EMAC management interface generates a full 32-bit preamble
• ST, Start of Frame (A "01" pattern indicates the start of frame)
• OP, Operation Code - A read instruction is indicated by "01", while a write instruction is indicated by "10"
• DEVAD, Device Address - A five-bit device address follows the opcode, with the most significant bit transmitted first.
• REGAD, Register Address - A five-bit register address follows the DEVAD field, with the most significant bit transmitted first. This field is used to access the management registers of the PHY.
• TA, Turnaround - The next two bit times are used to avoid contention on the MDIO port during a read transaction. For a read transaction, the PHY device and the system MDIO should be in tri-state for the first cycle of turnaround. The PHY device drives zero during the second cycle of the turnaround. For write transactions, the EMAC should drive 1 during the first cycle of the turnaround and zero during the second cycle.
• Data - The last 16 bits of the frame are the actual data bits. For a write operation, these bits are sent to the PHY device. For a read operation, the PHY device drives these bits. In both cases, the most significant bit is transmitted first.
• Idle - This indicates a high-impedance state of the MDIO line. The default state of the MDIO signal is high impedance with a pull-up resistor.

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global reset (asynchronous reset)
pi_clock	wire logic	input	Master MDIO reference clock
pi_master_mdio	wire logic	input	MDIO interface Master MDIO data input line (tri-state buffer outside of the module)
po_master_mdio	reg	output	Master MDIO data output line (tri-state buffer outside of the module)
po_master_oni	reg	output	Master MDIO direction tri-state buffer control (1 - Output, 0 - Input)
po_mdio_err	reg	output	Configuration interface (HOST clock domain) Indicates that a read from MDIO interface is invalid and the
pi_mdio_wdata	wire logic [15 : 0]	input	operation should be retried. This is indicated during a read turn-around cycle when the MDIO slave does not drive the MDIO signal to the low state. MDIO write data
po_mdio_rdata	reg [15 : 0]	output	MDIO read data
pi_mdio_start	wire logic	input	Setting this bit initiates an MDIO read/write operation. Start indication
po_mdio_done	reg	output	should remain asserted till the transaction complete. (asynchronous) MDIO transaction complete
pi_mdio_rnw	wire logic	input	This bit indicates the direction of the MDIO operation type:
pi_mdio_daddr	wire logic [4 : 0]	input	0 - MDIO Write operation, 1 - MDIO read operation This field is used to specify the device address to be accessed.
pi_mdio_raddr	wire logic [4 : 0]	input	This field is used to specify the register address to be accessed.

Always Blocks

always @ ( posedge pi_clock or negedge pi_reset )

MDIO State Machine

FSM Transitions for mdio_state

#	Current State	Next State	Condition	Comment
1	`PREAMBLE	`START	[(!(~ pi_reset) && (counter == 5'd0 && mdio_start == 1'b1))]
2	`PREAMBLE	`IDLE	[(!(~ pi_reset) && (counter == 5'd0))]
3	`START	`OPCODE	[(!(~ pi_reset) && (counter == 5'd0))]
4	`IDLE	`START	[(!(~ pi_reset) && (mdio_start == 1'b1))]
5	`OPCODE	`DEVADDR	[(!(~ pi_reset) && (counter == 5'd0))]
6	`DEVADDR	`REGADDR	[(!(~ pi_reset) && (counter == 5'd31))]
7	`REGADDR	`TURNAR	[(!(~ pi_reset) && (counter == 5'd31))]
8	`TURNAR	`PREAMBLE	[(!(~ pi_reset) && (counter == 5'd0 && pi_master_mdio != 1'b0 && pi_mdio_rnw == 1'b1))]
9	`TURNAR	`DATA	[(!(~ pi_reset) && !(counter == 5'd0 && pi_master_mdio != 1'b0 && pi_mdio_rnw == 1'b1) && (counter == 5'd0))]
10	`DATA	`PREAMBLE	[(!(~ pi_reset) && (counter == 5'd31))]

always @ ( posedge pi_clock or negedge pi_reset )

HOST to MDIO clock domain synchronization

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_mdio : ip_mac_mdio_g

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