Module ip_mac_tx_sync_g

ip_mac_tx_sync_g u_ip_mac_tx_sync_g ( .pi_tx_reset(pi_tx_reset), .pi_tx_f_clock(pi_tx_f_clock), .po_host_idone(po_host_idone), .pi_host_reset(pi_host_reset), .pi_host_clock(pi_host_clock), .pi_tx_stop(pi_tx_stop), .po_host_stop(po_host_stop), .pi_host_stop(pi_host_stop), .po_tx_stop(po_tx_stop), .pi_rx_fc_tx_off(pi_rx_fc_tx_off), .po_tx_fc_tx_off(po_tx_fc_tx_off), .pi_rx_fc_xoff(pi_rx_fc_xoff), .pi_rx_fc_xon(pi_rx_fc_xon), .po_tx_fc_xoff(po_tx_fc_xoff), .po_tx_fc_xon(po_tx_fc_xon) );

Block Diagram of ip_mac_tx_sync_g

The EMAC Transmit Synchronization module is responsible to synchronize all the control signals necessary to control the functionality of the transmit clock domain modules. Also the signals generated by the transmit modules and needed by the host clock domain modules are synchronized by the EMAC Transmit Synchronization module to host clock domain. In order to avoid the metastability of the output signal the synchronization from one clock domain to another will require two DFF's. The host and transmit clocks used by the synchronization module are free running clocks, since there is no possibility to generate synchronous wake-up's signals for gated clock module. Also this module is responsible to synchronize the reset done information (initialization done) used by the host DMA module in order to start data transfers.

Ports

Name	Type	Direction	Description
pi_tx_reset	wire logic	input	Transmit clock and reset Global Hardware/Software reset (transmit clock domain, active low)
pi_tx_f_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_host_idone	reg	output	Reset done Transmit initialization done (host clock domain)
pi_host_reset	wire logic	input	Host clock and reset Global Hardware/Software reset (host clock domain, active low)
pi_host_clock	wire logic	input	Host clock (from Clock Manager)
pi_tx_stop	wire logic	input	Inputs -> Synchronized outputs Transmit stop command acknowledge (transmit clock domain)
po_host_stop	reg	output	Transmit stop command acknowledge (synchronized to host clock domain)
pi_host_stop	wire logic	input	Transmit stop command (host clock domain)
po_tx_stop	reg	output	Transmit stop command (synchronized to transmit clock domain)
pi_rx_fc_tx_off	wire logic	input	Received transmit off command (receive clock domain)
po_tx_fc_tx_off	reg	output	Transmit off command (synchronized to transmit clock domain)
pi_rx_fc_xoff	wire logic	input	Receive FIFO level exceed high threshold, XOFF FC packet insert (receive clock domain)
pi_rx_fc_xon	wire logic	input	Transmit XOFF FC packet insert (synchronized to transmit clock domain)
po_tx_fc_xoff	reg	output	Receive FIFO level below low threshold, XON FC packet insert (receive clock domain)
po_tx_fc_xon	reg	output	Transmit XON FC packet insert (synchronized to transmit clock domain)

Always Blocks

always @ ( posedge pi_tx_f_clock or negedge pi_tx_reset )

Host to Transmit clock domain synchronization

always @ ( posedge pi_host_clock or negedge pi_host_reset )

Transmit to Host clock domain synchronization

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_tx_top : ip_mac_tx_top_g

      • tx_sync : ip_mac_tx_sync_g

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