Module ip_mac_tx_dpath_g

Block Diagram of ip_mac_tx_dpath_g

Ports
Name	Type	Direction	Description
pi_reset	wire logic	input	Global Software/Hardware Reset (transmit clock domain)
pi_g_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_err	wire logic	input	Signals comming in from the data FIFO related to data transfer Error indication
pi_data	wire logic [7 : 0]	input	Data bus (frame data 8-bit word)
pi_valid	wire logic	input	Valid data
pi_mac_state	wire logic [3 : 0]	input	MAC state
pi_en_high	wire logic	input	Enable High (MSB)
pi_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_burst_en	wire logic	input	Burst enable (valid only when operating mode is 1000 Mbps)
pi_half_duplex	wire logic	input	GMII Interface Half duplex operating mode
pi_gmii_col	wire logic	input	Collision indication (from PHY)
po_gmii_en	reg	output	Transmit MII/GMII enable indication (to PHY)
po_gmii_err	reg	output	Transmit MII/GMII error indication (to PHY)
po_gmii_data	reg [7 : 0]	output	Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY)
po_xmit_busy	reg	output	Used by the defering process (transmit enable ored with transmit error)

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset ) : GMII Output Signals Process

crc32_data8 ( logic[31:0] crc, logic[7:0] data ) : CRC: 32 DATA: 8, POLY: 104C11DB7 next crc