Module ip_async_fifo_g

ip_async_fifo_g #( .MEM_WIDTH(MEM_WIDTH) ) u_ip_async_fifo_g ( .pi_reset_wr(pi_reset_wr), .pi_reset_rd(pi_reset_rd), .pi_clock_wr(pi_clock_wr), .pi_clock_rd(pi_clock_rd), .pi_enable_wr(pi_enable_wr), .pi_enable_rd(pi_enable_rd), .po_full_wr(po_full_wr), .po_empty_rd(po_empty_rd), .po_last_wr(po_last_wr), .po_last_rd(po_last_rd), .pi_data_wr(pi_data_wr), .po_data_rd(po_data_rd) );

Block Diagram of ip_async_fifo_g

Asynchronous FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another.

Data words are placed into a FIFO buffer memory array by:

• control signals in one clock domain
• and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain.

Parameters

Name	Default	Description
MEM_WIDTH	32	Data width

Ports

Name	Type	Direction	Description
pi_reset_wr	wire logic	input	Write synchronous reset
pi_reset_rd	wire logic	input	Read synchronous reset
pi_clock_wr	wire logic	input	Write clock
pi_clock_rd	wire logic	input	Read clock
pi_enable_wr	wire logic	input	Write enable
pi_enable_rd	wire logic	input	Read enable
po_full_wr	reg	output	FIFO full indication
po_empty_rd	reg	output	FIFO empty indication
po_last_wr	reg	output	FIFO last location for write (almoast full)
po_last_rd	reg	output	FIFO last location for read (almoast empty)
pi_data_wr	wire logic [MEM_WIDTH - 1 : 0]	input	FIFO data input
po_data_rd	wire logic [MEM_WIDTH - 1 : 0]	output	FIFO data output

Always Blocks

always @ ( posedge pi_clock_wr )

Data Path - Input Selection Process

always @ ( ring_wr or pi_enable_wr )

Assert ready write signal according with the write address value

always @ ( posedge pi_clock_wr or negedge pi_reset_wr )

Write Pointer Updated when Write Access is performed

always @ ( ring_rd or pi_enable_rd )

assert ready read signal according with the read address value

always @ ( posedge pi_clock_rd or negedge pi_reset_rd )

Read Pointer Updated when Read Access is performed *

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • rx_async : ip_async_fifo_g #(.MEM_WIDTH(37))

    • mac_tx_top : ip_mac_tx_top_g

      • tx_data_async : ip_async_fifo_g #(.MEM_WIDTH(39))

      • tx_stat_async : ip_async_fifo_g #(.MEM_WIDTH(10))

Submodules

• ip_async_fifo_g #(.MEM_WIDTH(37))

  • cell_0 : ip_sync_cell

  • cell_1 : ip_sync_cell

  • cell_2 : ip_sync_cell

  • cell_3 : ip_sync_cell

  • cell_4 : ip_sync_cell

  • cell_5 : ip_sync_cell

  • cell_6 : ip_sync_cell

  • cell_7 : ip_sync_cell

• ip_async_fifo_g #(.MEM_WIDTH(39))

  • cell_0 : ip_sync_cell

  • cell_1 : ip_sync_cell

  • cell_2 : ip_sync_cell

  • cell_3 : ip_sync_cell

  • cell_4 : ip_sync_cell

  • cell_5 : ip_sync_cell

  • cell_6 : ip_sync_cell

  • cell_7 : ip_sync_cell

• ip_async_fifo_g #(.MEM_WIDTH(10))

  • cell_0 : ip_sync_cell

  • cell_1 : ip_sync_cell

  • cell_2 : ip_sync_cell

  • cell_3 : ip_sync_cell

  • cell_4 : ip_sync_cell

  • cell_5 : ip_sync_cell

  • cell_6 : ip_sync_cell

  • cell_7 : ip_sync_cell

Schematic Diagram of ip_async_fifo_g

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