Module ip_mac_cfg_hash_g

ip_mac_cfg_hash_g u_ip_mac_cfg_hash_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_g_clock(pi_g_clock), .po_en_clock(po_en_clock), .pi_wakeup(pi_wakeup), .pi_wr_data(pi_wr_data), .pi_wr_setup(pi_wr_setup), .pi_hash_nfix(pi_hash_nfix), .pi_little(pi_little), .po_wr_en(po_wr_en), .po_wr_data(po_wr_data), .po_wr_addr(po_wr_addr) );

Block Diagram of ip_mac_cfg_hash_g

A special configuration sequence must be performed before the reception process is started, except when it operates in promiscuous filtering mode. This is done by successively writing to CRFT configuration register. Depending on the selected filtering mode (CSR6[5:4] Filtering status field), the appropriate information should be written into the CRFT (see EMAC Functional Specification 1.1)

When hash multicast or hash filtering operating mode is selected, 16 consecutive writes should be performed to the CRFT register, representing the 512-bit hash table information. After completing the hash table write, two additional writes should be performed on CRFT encapsulating the perfect 48-bit MAC address used for exact physical destination address match processing.

When perfect filtering mode is selected 32 consecutive writes should be performed to the CRFT register encapsulating 16 exact match addresses.

The structure of each 32 bit word written to CRFT register depends on CSR0[7] (Big/Little Endian field) and CSR6[5:4] (Filtering status field). See 9.2.1 and 9.2.2 for a detailed description of CRFT configuration sequence.

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Hardware Reset (host clock domain)
pi_f_clock	wire logic	input	Free HOST interface clock signal
pi_g_clock	wire logic	input	Gated HOST interface clock signal
po_en_clock	reg	output	Enable HOST interface clock signal
pi_wakeup	wire logic	input	From/To Receive DMA Wake-up internal clock used by the Setup Frame FSM,
pi_wr_data	wire logic [31 : 0]	input	should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be de-asserted 2 clock cycles after Setup Frame complete Setup Frame data (HOST clock synchronous)
pi_wr_setup	wire logic	input	Setup Frame write enable (HOST clock synchronous)
pi_hash_nfix	wire logic	input	Configuration Hash filtering + 1 Address match / 16 Address match
pi_little	wire logic	input	Little endian
po_wr_en	reg [1 : 0]	output	Hash Table Memory access Hash table write enable
po_wr_data	reg [47 : 0]	output	Hash table write data
po_wr_addr	reg [3 : 0]	output	Hash table write address

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

FC Data Out Process

always @ ( posedge pi_f_clock or negedge pi_reset )

Gated Clock Enable

FSM Transitions for fsm_hash_st

#	Current State	Next State	Condition	Comment
1	`IDLE	`WRITE_1	[(!(~ pi_reset) && (pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b0)), (!(~ pi_reset) && !(pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b0) && (pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b1))]
2	`WRITE_1	`IDLE	[(!(~ pi_reset) && (pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b0))]
3	`WRITE_1	`WRITE_2	[(!(~ pi_reset) && !(pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b0) && (pi_wr_setup == 1'b1 && pi_hash_nfix == 1'b1) && (po_wr_addr == 4'hf))]
4	`WRITE_2	`WRITE_3	[(!(~ pi_reset) && (pi_wr_setup == 1'b1))]
5	`WRITE_3	`WRITE_4	[(!(~ pi_reset) && (pi_wr_setup == 1'b1))]
6	`WRITE_4	`IDLE	[!(~ pi_reset)]

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • cfg_hash : ip_mac_cfg_hash_g

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