Module ip_mac_dram_003

MEM_ADDRMEM_WIDTHpi_clock_wrlogicpi_clock_rdlogicpi_addr_wr[MEM_ADDR-1:0]logicpi_addr_rd[MEM_ADDR-1:0]logicpi_wr_enlogicpi_data_wr[MEM_WIDTH-1:0]logicpo_data_rdlogic[MEM_WIDTH-1:0]

Block Diagram of ip_mac_dram_003

The internal DRAM memory modules have the property that when the read address selects a memory location, this location is write protected (locked for write operation). Since when FIFO is empty both read and write addresses points to the same address and the a write operation should be performed, the read memory address should point to an unused memory location in order to unlock the write operation. Moving the internal address to an unused location when write enable modifies the read operation timing since the read DRAM address does not point to the right read address. In order to avoid the timing read response delay a bypass register between input and output data is used. When FIFO is empty the output data reads the bypass register instead of DRAM memory output.

Note: No bypass is necessary for Hash table memory since the read is not performed in the same time memory is writed. Bypass data register and bypass select multiplexer is removed from this module

Parameters

Name

Default

Description

MEM_ADDR

4

Address width (9 -> 512 locations, 10->1024)

MEM_WIDTH

16

Data width

Ports

Name

Type

Direction

Description

pi_clock_wr

wire logic

input

Input write clock (multiplexed with scan clock ouside this module)

pi_clock_rd

wire logic

input

Input read clock

pi_addr_wr

wire logic [MEM_ADDR - 1 : 0]

input

Write address

pi_addr_rd

wire logic [MEM_ADDR - 1 : 0]

input

Read address

pi_wr_en

wire logic

input

Write enable

pi_data_wr

wire logic [MEM_WIDTH - 1 : 0]

input

Write data

po_data_rd

wire logic [MEM_WIDTH - 1 : 0]

output

Read data

Always Blocks

always @ ( pi_wr_en or pi_addr_rd or pi_addr_wr )

Read Pointer Move (when read pointer equal write pointer and write enable the read memory address should not point to the writed location)

Instances

Submodules

  • ip_mac_dram_003 #(.MEM_ADDR(4), .MEM_WIDTH(16))
    • dram_001 : dram_001 #(.MEM_ADDR(4), .MEM_WIDTH(16))

dram_001 (dram_001) wr_clk rd_clk addr_wr addr_rd wr_en data_wr data_rd read_addr pi_addr_rd pi_wr_en pi_addr_wr rx_dram_hash_1 (ip_mac_dram_003) pi_clock_wr pi_clock_rd pi_addr_wr pi_addr_rd pi_wr_en pi_data_wr po_data_rd

Schematic Diagram of ip_mac_dram_003