Module ip_mac_hostif_rx

Block Diagram of ip_mac_hostif_rx

Ports
Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous pi_reset
pi_g_clock	wire logic	input	host gated clock
pi_f_clock	wire logic	input	host free clock
po_en_clock	reg	output	enable clock condition
po_rx_enable_rd	wire logic	output	RX FIFO interface rx fifo read command
pi_rx_empty	wire logic	input	rx fifo full
pi_rx_last_rd	wire logic	input	rx fifo almost full
pi_rx_data	wire logic [31 : 0]	input	rx fifo data
pi_rx_sof	wire logic	input	rx fifo eof
pi_rx_eof	wire logic	input	rx fifo eof
rx_ds_addr_valid	wire logic	input	ip_mac_hostif_rxds from ip_mac_hostif_rxds (currently fetched descriptor address valid)
rx_ds_next_addr	wire logic [31 : 0]	input	from ip_mac_hostif_rxds (currently fetched descriptor address)
rx_valid_ds_read	reg	output
po_rx_ds1	wire logic [1 : 0]	output	mapped to rx, rx_ds1[25:24]
po_rx_ds3	wire logic [31 : 0]	output
rx_req	reg	output	arbiter
rx_allowed	wire logic	input
rx_mcmd	reg [1 : 0]	output
rx_maddr	reg [31 : 0]	output
rx_mdata	reg [31 : 0]	output
rx_mlast	reg	output
pi_host_sdva	wire logic	input	host interface
pi_host_sdata	wire logic [31 : 0]	input
pi_regs_csr14_sr	wire logic	input	ip_mac_regs_bank (config)
pi_config_burst_size	wire logic [5 : 0]	input	limit for the rx,tx burst transfers
po_regs_csr5_ri	reg	output
po_regs_csr5_ovf	reg	output
po_regs_csr5_rwt	reg	output

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset ) : state machine for rx descriptor based transfer

FSM Transitions for rx_state
#	Current State	Next State	Condition
1	`RX_IDLE	`RX_READ_DS	[(!(~ pi_reset) && !(! rx_ds_addr_valid) && !(rx_ds_addr_valid && ! rx_req) && (rx_allowed))]
2	`RX_READ_DS	`RX_WRITE_PAUSE	[(!(~ pi_reset) && (pi_host_sdva) && !(rx_burst_cnt == 0) && !(rx_burst_cnt == 1) && (rx_burst_cnt == 2))]
3	`RX_WRITE_PAUSE	`RX_IDLE	[(!(~ pi_reset) && (! rx_ds_valid))]
4	`RX_WRITE_PAUSE	`RX_WRITE	[(!(~ pi_reset) && !(! rx_ds_valid) && !(! pi_rx_empty && ! pi_rx_last_rd && ! rx_req) && (rx_allowed))]
5	`RX_WRITE	`RX_STAT	[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && (rx_frame_complete))]
6	`RX_WRITE	`RX_WRITE_DS	[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && !(! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))]
7	`RX_WRITE	`RX_WRITE_PAUSE	[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && (rx_burst_complete)), (!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && !(rx_burst_complete)), (!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && (! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))]
8	`RX_STAT	`RX_WRITE_DS	[(!(~ pi_reset) && (! pi_rx_empty))]
9	`RX_WRITE_DS	`RX_IDLE	[(!(~ pi_reset) && (rx_allowed && pi_host_sdva))]