Module ip_synchronous_fifo

MEM_ADDRpi_resetlogicpi_clocklogicpi_wr_enlogicpi_rd_enlogicpo_rd_addrlogic[MEM_ADDR-1:0]po_wr_addrlogic[MEM_ADDR-1:0]po_fulllogicpo_emptylogicpo_overflowlogicpo_underflowlogic

Block Diagram of ip_synchronous_fifo

Parameters

Name

Default

Description

MEM_ADDR

6

Transmit memory address width (9 -> 512 locations, 10->1024)

Ports

Name

Type

Direction

Description

pi_reset

wire logic

input

pi_clock

wire logic

input

po_rd_addr

wire logic [MEM_ADDR - 1 : 0]

output

po_wr_addr

wire logic [MEM_ADDR - 1 : 0]

output

pi_wr_en

wire logic

input

pi_rd_en

wire logic

input

po_full

wire logic

output

po_empty

wire logic

output

po_overflow

wire logic

output

po_underflow

wire logic

output

Always Blocks

always @ ( posedge pi_clock or negedge pi_reset )

Read Address Update Process

always @ ( posedge pi_clock or negedge pi_reset )

Write Address Update Process