Module ip_synchronous_fifo

ip_synchronous_fifo #( .MEM_ADDR(MEM_ADDR) ) u_ip_synchronous_fifo ( .pi_reset(pi_reset), .pi_clock(pi_clock), .po_rd_addr(po_rd_addr), .po_wr_addr(po_wr_addr), .pi_wr_en(pi_wr_en), .pi_rd_en(pi_rd_en), .po_full(po_full), .po_empty(po_empty), .po_overflow(po_overflow), .po_underflow(po_underflow) );

Block Diagram of ip_synchronous_fifo

Parameters

Name	Default	Description
MEM_ADDR	6	Transmit memory address width (9 -> 512 locations, 10->1024)

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input
pi_clock	wire logic	input
po_rd_addr	wire logic [MEM_ADDR - 1 : 0]	output
po_wr_addr	wire logic [MEM_ADDR - 1 : 0]	output
pi_wr_en	wire logic	input
pi_rd_en	wire logic	input
po_full	wire logic	output
po_empty	wire logic	output
po_overflow	wire logic	output
po_underflow	wire logic	output

Always Blocks

always @ ( posedge pi_clock or negedge pi_reset )

Read Address Update Process

always @ ( posedge pi_clock or negedge pi_reset )

Write Address Update Process

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