Module ip_mac_rx_gmii_g

ip_mac_rx_gmii_g u_ip_mac_rx_gmii_g ( .pi_loopback(pi_loopback), .pi_tx_gmii_val(pi_tx_gmii_val), .pi_tx_gmii_err(pi_tx_gmii_err), .pi_tx_gmii_data(pi_tx_gmii_data), .pi_gmii_val(pi_gmii_val), .pi_gmii_data(pi_gmii_data), .pi_gmii_err(pi_gmii_err), .po_gmii_val(po_gmii_val), .po_gmii_data(po_gmii_data), .po_gmii_err(po_gmii_err) );

Block Diagram of ip_mac_rx_gmii_g

The EMAC Receive MII/GMII module is responsible to multiplex the MII input interface (nibble oriented) signals coming from physical layer into GMII format when 10/100 Mbps operating mode is selected or to pass the GMII signal to the EMAC Receive State Machine when operating speed above 100 Mbps.

The EMAC Receive MII/GMII module it also checks for invalid Ethernet MAC frames by checking for proper byte-boundary alignment of the end of the frame. The block is responsible to generate the alignment error indication when frame length is not an integer number of bytes.

The module is also responsible for the internal loop-back operation, when the EMAC operates in loop-back mode. The EMAC Clock Manager module is responsible to switch between the input receive clock and transmit clock for loop-back operation.

Ports

Name	Type	Direction	Description
pi_loopback	wire logic	input	Loopback mode select
pi_tx_gmii_val	wire logic	input	Loopback Info Loopback MII/GMII data valid indication (from TX)
pi_tx_gmii_err	wire logic	input	Loopback MII/GMII error indication (from TX)
pi_tx_gmii_data	wire logic [7 : 0]	input	Loopback MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from TX)
pi_gmii_val	wire logic	input	gmii Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (from PHY)
pi_gmii_data	wire logic [7 : 0]	input	Receive MII/GMII error indication (from PHY)
pi_gmii_err	wire logic	input	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY)
po_gmii_val	wire logic	output	GMII Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (to RX state)
po_gmii_data	wire logic [7 : 0]	output	Receive MII/GMII error indication (to RX state)
po_gmii_err	wire logic	output	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (to RX state)

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • rx_gmii : ip_mac_rx_gmii_g

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