Module ip_mac_tx_top_g

TX_MEM_ADDRpi_tx_resetlogicpi_host_resetlogicpi_tx_f_clocklogicpi_tx_g_clock[3:0]logicpi_host_stop_xmitlogicpi_rx_fc_xoff_tgllogicpi_rx_fc_xon_tgllogicpi_tx_xoff_value[15:0]logicpi_tx_xon_value[15:0]logicpi_tx_col_limit[4:0]logicpi_tx_fc_enablelogicpi_rx_fc_tx_offlogicpi_tx_gigabitlogicpi_tx_burst_lim[15:0]logicpi_tx_burst_enlogicpi_tx_half_duplexlogicpi_tx_ifg_cfg_1[7:0]logicpi_tx_ifg_cfg_2[7:0]logicpi_tx_store_fwdlogicpi_tx_threshold[TX_MEM_ADDR-1:0]logicpi_gmii_collogicpi_gmii_crslogicpi_host_stat_readlogicpi_host_clocklogicpi_host_littlelogicpi_host_enable_wrlogicpi_host_data_wr[31:0]logicpi_host_byte_wr[1:0]logicpi_host_start_wrlogicpi_host_end_wrlogicpi_host_error_wrlogicpi_host_pad_wrlogicpi_host_crc_wrlogicpo_tx_en_clocklogic[3:0]po_host_init_donelogicpo_host_stop_xmitlogicpo_tx_xmit_nfclogicpo_gmii_enlogicpo_gmii_errlogicpo_gmii_datalogic[7:0]po_host_stat_emptylogicpo_host_stat_lastlogicpo_host_stat_datalogic[9:0]po_host_full_wrlogicpo_host_last_wrlogic

Block Diagram of ip_mac_tx_top_g

Parameters

Name

Default

Description
TX_MEM_ADDR

9

Transmit memory address width (9 -> 512 locations, 10->1024)
Ports

Name

Type

Direction

Description
pi_tx_reset

wire logic

input

Global Software/Hardware Reset (transmit clock domain)
pi_host_reset

wire logic

input

Global Software/Hardware Reset (host clock domain)
pi_tx_f_clock

wire logic

input

Transmit clock Free Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_tx_g_clock

wire logic [3 : 0]

input

Gated Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_tx_en_clock

wire logic [3 : 0]

output

Enable Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable
po_host_init_done

wire logic

output

Initialisation done Transmit initialisation done (host clock domain)
pi_host_stop_xmit

wire logic

input

Start/Stop transmit process Transmit EMAC stop command
po_host_stop_xmit

wire logic

output

Transmit EMAC stopped

pi_rx_fc_xoff_tgl

wire logic

input

Configuration Interface
from RX EMAC insert XOFF flow control information
pi_rx_fc_xon_tgl

wire logic

input

from RX EMAC insert XON flow control information
pi_tx_xoff_value

wire logic [15 : 0]

input

from configuration XOFF flow control pause value

pi_tx_xon_value

wire logic [15 : 0]

input

from configuration XON flow control pause value

pi_tx_col_limit

wire logic [4 : 0]

input

Half Duplex back presure collision limit

pi_tx_fc_enable

wire logic

input

(maximum collision number during back presure algorithm) Transmit flow control enable
pi_rx_fc_tx_off

wire logic

input

Flow control Stop transmit commang (flow control received)
pi_tx_gigabit

wire logic

input

Operating 1000 Mbps (Gigabit) mode
pi_tx_burst_lim

wire logic [15 : 0]

input

Burst limit (valid only when operating mode is 1000 Mbps)

pi_tx_burst_en

wire logic

input

Burst enable (valid only when operating mode is 1000 Mbps)

pi_tx_half_duplex

wire logic

input

Operating Half Duplex mode
pi_tx_ifg_cfg_1

wire logic [7 : 0]

input

Interframe gap part 1 (usualy 2/3 from IFG)

pi_tx_ifg_cfg_2

wire logic [7 : 0]

input

Interframe gap part 2 (usualy 1/3 from IFG)

pi_tx_store_fwd

wire logic

input

Store and Forward transmit FIFO operating mode

pi_tx_threshold

wire logic [TX_MEM_ADDR - 1 : 0]

input

Cut Trough (pi_emac_store_fwd not asserted) FIFO threshold

po_tx_xmit_nfc

wire logic

output

GMII/MII interface
Transmit FSM data frame transmit enable (transmit clock domain)
po_gmii_en

wire logic

output

NOTE: This signal is not asserted during flow control frame transmission Transmit MII/GMII enable indication (to PHY)
po_gmii_err

wire logic

output

Transmit MII/GMII error indication (to PHY)
po_gmii_data

wire logic [7 : 0]

output

Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY)
pi_gmii_col

wire logic

input

Collision indication (from PHY)
pi_gmii_crs

wire logic

input

Carrier Sense indication (from PHY)
pi_host_stat_read

wire logic

input

Read statistic word command
po_host_stat_empty

wire logic

output

Statistic FIFO not empty
po_host_stat_last

wire logic

output

Last statistic word indication

po_host_stat_data

wire logic [9 : 0]

output

Statistic TDES0 word data
pi_host_clock

wire logic

input

HOST interface
HOST interface clock signal
pi_host_little

wire logic

input

Little endian (data path organisation)
pi_host_enable_wr

wire logic

input

Transmit MAC data path, HOST enable command

po_host_full_wr

wire logic

output

Transmit MAC data path, HOST FIFO full indication
po_host_last_wr

wire logic

output

Transmit MAC data path, HOST FIFO last location indication
pi_host_data_wr

wire logic [31 : 0]

input

Transmit MAC data path, HOST data (transmit data)
pi_host_byte_wr

wire logic [1 : 0]

input

Transmit MAC data path, HOST byte enable (transmit data byte enable)
pi_host_start_wr

wire logic

input

Transmit MAC data path, HOST start of frame indication
pi_host_end_wr

wire logic

input

Transmit MAC data path, HOST start of frame indication
pi_host_error_wr

wire logic

input

Unused please check if useful (if not remove)
pi_host_pad_wr

wire logic

input

Transmit MAC data path, HOST padding enable (valid only when pi_host_end_wr)
pi_host_crc_wr

wire logic

input

Transmit MAC data path, HOST crc enable (valid only when pi_host_end_wr)

Instances

Submodules

tx_bkoff (ip_mac_tx_bkoff_g) pi_reset pi_g_clock pi_f_clock po_en_clock pi_bk_reset pi_bk_start pi_half_duplex pi_hd_fc_enable po_bk_done tx_data_async (ip_async_fifo_g) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd pi_enable_wr pi_enable_rd po_full_wr po_empty_rd po_last_wr po_last_rd pi_data_wr po_data_rd tx_data_dram (ip_mac_dram_001) pi_clock_wr pi_clock_rd pi_addr_wr pi_addr_rd pi_wr_en pi_data_wr po_data_rd tx_dpath (ip_mac_tx_dpath_g) pi_reset pi_g_clock pi_err pi_data pi_valid pi_mac_state pi_en_high pi_gigabit pi_burst_en pi_half_duplex pi_gmii_col po_gmii_en po_gmii_err po_gmii_data po_xmit_busy tx_dsplit (ip_mac_tx_dsplit_g) pi_reset pi_g_clock pi_f_clock po_en_clock pi_data pi_sop pi_eop pi_err pi_pad pi_crc pi_byte pi_wr_addr po_fc_addr pi_half_duplex po_rd_ptr po_rd_addr po_fc_req po_data_req pi_fc_ack pi_data_ack pi_fc_data pi_fc_ready pi_fc_tx_off pi_fc_sop pi_fc_eop pi_read pi_remove pi_reload pi_update pi_en_high po_data po_sop po_eop po_err po_pad po_crc po_valid tx_endian (ip_mac_big_endian) pi_little pi_data po_data tx_fc_gen (ip_mac_fc_gen_g) pi_reset pi_g_clock pi_f_clock po_en_clock pi_fc_addr pi_fc_enable pi_xon_value pi_xoff_value pi_fc_xon_tgl pi_fc_xoff_tgl pi_half_duplex pi_col_limit pi_gmii_col po_hd_fc_en po_fc_ready po_fc_eop po_fc_sop po_fc_data tx_fifo (ip_mac_tx_fifo_g) pi_reset pi_f_clock pi_empty_rd pi_last_rd po_enable_rd pi_rd_addr po_wr_addr po_wr_en po_wr_ptr pi_store_fwd pi_threshold pi_end_of_pkt tx_fsm (ip_mac_tx_fsm_g) pi_reset pi_g_clock pi_f_clock po_en_clock pi_sop pi_eop pi_pad pi_crc pi_valid pi_fc_req pi_data_req po_fc_ack po_data_ack po_read po_remove po_reload po_mac_state po_update po_en_high pi_half_duplex pi_hd_fc_en pi_stop_xmit po_stop_xmit po_bk_reset po_bk_start pi_bk_done pi_deferring pi_deferred pi_gigabit pi_burst_lim pi_burst_en po_burst_en pi_gmii_en pi_gmii_col pi_gmii_crs po_xmit_nfc pi_stat_full po_stat_data po_stat_load tx_gmii (ip_mac_tx_gmii_g) pi_reset pi_f_clock pi_gigabit pi_half_duplex pi_burst_en pi_ifg_cfg_1 pi_ifg_cfg_2 po_deferring po_deferred pi_gmii_busy pi_gmii_en pi_gmii_err po_gmii_crs pi_gmii_crs pi_gmii_col tx_stat_async (ip_async_fifo_g) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd pi_enable_wr pi_enable_rd po_full_wr po_empty_rd po_last_wr po_last_rd pi_data_wr po_data_rd tx_sync (ip_mac_tx_sync_g) pi_tx_reset pi_tx_f_clock po_host_idone pi_host_reset pi_host_clock pi_tx_stop po_host_stop pi_host_stop po_tx_stop pi_rx_fc_tx_off po_tx_fc_tx_off pi_rx_fc_xoff pi_rx_fc_xon po_tx_fc_xoff po_tx_fc_xon {pi_host_start_wr, pi_host_end_wr, pi_host_error_wr, pi_host_byte_wr, pi_host_pad_wr, pi_host_crc_wr, host_data_wr} host_data_wr pi_host_crc_wr pi_host_pad_wr pi_host_byte_wr pi_host_error_wr pi_host_end_wr pi_host_start_wr tx_mac_rd_data {tx_mac_rd_start, tx_mac_rd_end, tx_mac_rd_error, tx_mac_rd_byte, tx_mac_rd_pad, tx_mac_rd_crc, tx_mac_rd_data} tx_mac_rd_crc tx_mac_rd_pad tx_mac_rd_byte tx_mac_rd_error tx_mac_rd_end tx_mac_rd_start mac_tx_top (ip_mac_tx_top_g) pi_tx_reset pi_host_reset pi_tx_f_clock pi_tx_g_clock po_tx_en_clock po_host_init_done pi_host_stop_xmit po_host_stop_xmit pi_rx_fc_xoff_tgl pi_rx_fc_xon_tgl pi_tx_xoff_value pi_tx_xon_value pi_tx_col_limit pi_tx_fc_enable pi_rx_fc_tx_off pi_tx_gigabit pi_tx_burst_lim pi_tx_burst_en pi_tx_half_duplex pi_tx_ifg_cfg_1 pi_tx_ifg_cfg_2 pi_tx_store_fwd pi_tx_threshold po_tx_xmit_nfc po_gmii_en po_gmii_err po_gmii_data pi_gmii_col pi_gmii_crs pi_host_stat_read po_host_stat_empty po_host_stat_last po_host_stat_data pi_host_clock pi_host_little pi_host_enable_wr po_host_full_wr po_host_last_wr pi_host_data_wr pi_host_byte_wr pi_host_start_wr pi_host_end_wr pi_host_error_wr pi_host_pad_wr pi_host_crc_wr

Schematic Diagram of ip_mac_tx_top_g