Module ip_mac_host_if

ip_mac_host_if u_ip_mac_host_if ( .pi_reset(pi_reset), .pi_sw_reset(pi_sw_reset), .pi_clock(pi_clock), .pi_factor(pi_factor), .pi_base_address(pi_base_address), .po_host_mcmd(po_host_mcmd), .po_host_maddr(po_host_maddr), .po_host_mdata(po_host_mdata), .po_host_mlast(po_host_mlast), .pi_host_sdata(pi_host_sdata), .pi_host_sdva(pi_host_sdva), .pi_host_serr(pi_host_serr), .po_rx_enable_rd(po_rx_enable_rd), .pi_rx_empty(pi_rx_empty), .pi_rx_last_rd(pi_rx_last_rd), .pi_rx_data(pi_rx_data), .pi_rx_sof(pi_rx_sof), .pi_rx_eof(pi_rx_eof), .pi_rx_err(pi_rx_err), .pi_rx_be(pi_rx_be), .po_tx_enable_wr(po_tx_enable_wr), .pi_tx_full(pi_tx_full), .pi_tx_last_wr(pi_tx_last_wr), .po_tx_data(po_tx_data), .po_tx_be(po_tx_be), .po_tx_sof(po_tx_sof), .po_tx_eof(po_tx_eof), .po_tx_put_crc(po_tx_put_crc), .po_tx_put_padding(po_tx_put_padding), .po_tx_upd_read(po_tx_upd_read), .pi_tx_upd_empty(pi_tx_upd_empty), .pi_tx_upd_last(pi_tx_upd_last), .pi_tx_upd_data(pi_tx_upd_data), .pi_regs_csr0_tap(pi_regs_csr0_tap), .pi_regs_csr0_ape(pi_regs_csr0_ape), .pi_regs_csr0_bar(pi_regs_csr0_bar), .pi_regs_csr15_swr(pi_regs_csr15_swr), .pi_regs_csr1_tpd(pi_regs_csr1_tpd), .pi_regs_csr2_rpd(pi_regs_csr2_rpd), .pi_regs_csr3_stl(pi_regs_csr3_stl), .pi_regs_csr4_srl(pi_regs_csr4_srl), .po_regs_csr5_rs(po_regs_csr5_rs), .pi_regs_csr5_rwt(pi_regs_csr5_rwt), .po_regs_csr5_rps(po_regs_csr5_rps), .po_regs_csr5_ru(po_regs_csr5_ru), .po_regs_csr5_tu(po_regs_csr5_tu), .po_regs_csr5_ri(po_regs_csr5_ri), .po_regs_csr5_tjt(po_regs_csr5_tjt), .pi_regs_csr15_st(pi_regs_csr15_st), .pi_regs_csr15_sr(pi_regs_csr15_sr), .po_regs_csr8_mfc_inc(po_regs_csr8_mfc_inc), .pi_config_burst_size(pi_config_burst_size), .pi_config_ds_offset(pi_config_ds_offset), .pi_test_en(pi_test_en), .pi_test_clk(pi_test_clk), .pi_scan_en(pi_scan_en), .pi_scan_in(pi_scan_in), .po_scan_out(po_scan_out) );

Block Diagram of ip_mac_host_if

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous reset
pi_sw_reset	wire logic	input	software reset
pi_clock	wire logic	input	host clock
pi_factor	wire logic	input	host clock enable
pi_base_address	wire logic [23 : 0]	input	HOST Interface device int mem space base address
po_host_mcmd	reg [1 : 0]	output	command
po_host_maddr	reg [31 : 0]	output	address
po_host_mdata	reg [31 : 0]	output	data to write
po_host_mlast	reg	output	last word
pi_host_sdata	wire logic [31 : 0]	input	data to read
pi_host_sdva	wire logic	input	data valid
pi_host_serr	wire logic	input	error during last transaction
po_rx_enable_rd	wire logic	output	RX FIFO interface rx fifo read command
pi_rx_empty	wire logic	input	rx fifo full
pi_rx_last_rd	wire logic	input	rx fifo almost full
pi_rx_data	wire logic [31 : 0]	input	rx fifo data
pi_rx_sof	wire logic	input	rx fifo eof
pi_rx_eof	wire logic	input	rx fifo eof
pi_rx_err	wire logic	input	rx fifo error
pi_rx_be	wire logic [1 : 0]	input	rx fifo data byte enable
po_tx_enable_wr	wire logic	output	rx fifo read command
pi_tx_full	wire logic	input	rx fifo full
pi_tx_last_wr	wire logic	input	rx fifo almost full
po_tx_data	wire logic [31 : 0]	output	rx fifo data
po_tx_be	wire logic [1 : 0]	output	tx fifo data byte enable
po_tx_sof	wire logic	output	tx fifo start of frame
po_tx_eof	wire logic	output	tx fifo end of frame
po_tx_put_crc	wire logic	output	put crc indication (valid only when sof=1)
po_tx_put_padding	wire logic	output	put padding indication (valid only when sof=1)
po_tx_upd_read	wire logic	output	TX update fifo interface
pi_tx_upd_empty	wire logic	input
pi_tx_upd_last	wire logic	input
pi_tx_upd_data	wire logic [9 : 0]	input
pi_regs_csr0_tap	wire logic [15 : 0]	input	Registers bank interface tx automatic polling period CSR0[31:16]
pi_regs_csr0_ape	wire logic	input	tx auto polling enable CSR[15]
pi_regs_csr0_bar	wire logic	input	bus arbitration
pi_regs_csr15_swr	wire logic	input	software reset
pi_regs_csr1_tpd	wire logic	input	transmit poll demand
pi_regs_csr2_rpd	wire logic	input	receive poll demand
pi_regs_csr3_stl	wire logic [29 : 0]	input	transmit descriptor base address
pi_regs_csr4_srl	wire logic [29 : 0]	input	receive descriptor base address
po_regs_csr5_rs	wire logic [1 : 0]	output	receive process state
pi_regs_csr5_rwt	wire logic	input	receive watchdog timeout
po_regs_csr5_rps	wire logic	output	receive process stopped
po_regs_csr5_ru	reg	output	receive buffer unavailable
po_regs_csr5_tu	reg	output	transmit buffer unavailable
po_regs_csr5_ri	wire logic	output	receive interupt
po_regs_csr5_tjt	reg	output	signals Transmit jabber timeout error to the CSR5 register; this will signal to the HOST to perform a software reset to the EMAC
pi_regs_csr15_st	wire logic	input	start/stop transmit
pi_regs_csr15_sr	wire logic	input	start / stop receive
po_regs_csr8_mfc_inc	wire logic	output	missed frame counter increment command
pi_config_burst_size	wire logic [5 : 0]	input	limit for the rx,tx burst transfers
pi_config_ds_offset	wire logic [4 : 0]	input	pi_rx_mac_ds_poll, //from the RX EMAC part (new frame arrived, or new data arrived) offset to increment the address if a descriptor
pi_test_en	wire logic	input	Test and Scan interface signals Test enable
pi_test_clk	wire logic	input	Test clock
pi_scan_en	wire logic	input	SCAN chain shift enable
pi_scan_in	wire logic	input	SCAN chain input
po_scan_out	wire logic	output	SCAN chain output

Always Blocks

always @ ( posedge clock or negedge reset )

manages the next descriptor aquire when rx_ds_needed is asserted, asserts rx_ds_req when pi_host_arb_ds_dv is asserted load pi_host_arb_ds_data into current_ds_addr and deasserts po_host_arb_ds_req the one that asserted ds_needed waits for pi_host_arb_ds_dv to reset

FSM Transitions for rx_ds_state

#	Current State	Next State	Condition	Comment
1	`RX_DS_IDLE	`RX_DS_MAIN	[!(! pi_regs_csr15_sr)]
2	`RX_DS_MAIN	`RX_DS_READ	[(rx_ds_allowed)]
3	`RX_DS_READ	`RX_DS_WAIT	[((pi_host_sdva) && (pi_host_sdata[31]))]
4	`RX_DS_READ	`RX_DS_SUSPEND	[((pi_host_sdva) && !(pi_host_sdata[31]))]
5	`RX_DS_WAIT	`RX_DS_MAIN	[(rx_valid_ds_read)]
6	`RX_DS_SUSPEND	`RX_DS_MAIN	[(rx_mac_ds_poll || pi_regs_csr2_rpd)]

always @ ( posedge clock or negedge reset )

FSM Transitions for rx_state

#	Current State	Next State	Condition	Comment
1	`RX_IDLE	`RX_READ_DS	[(rx_allowed)]
2	`RX_READ_DS	`RX_WRITE_PAUSE	[((pi_host_sdva) && !(rx_burst_cnt == 0) && !(rx_burst_cnt == 1) && (rx_burst_cnt == 2))]
3	`RX_WRITE_PAUSE	`RX_IDLE	[(! rx_ds_valid)]
4	`RX_WRITE_PAUSE	`RX_WRITE	[(!(! rx_ds_valid) && !(! pi_rx_empty && ! pi_rx_last_rd && ! rx_req) && (rx_allowed))]
5	`RX_WRITE	`RX_STAT	[(!(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && (rx_frame_complete))]
6	`RX_WRITE	`RX_WRITE_DS	[(!(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && !(! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))]
7	`RX_WRITE	`RX_WRITE_PAUSE	[(!(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && (rx_burst_complete)), (!(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && !(rx_burst_complete)), (!(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && (! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))]
8	`RX_STAT	`RX_WRITE_DS	[(! pi_rx_empty)]
9	`RX_WRITE_DS	`RX_IDLE	[(rx_allowed && pi_host_sdva)]

always @ ( posedge clock or negedge reset )

manages the next descriptor aquire

FSM Transitions for tx_ds_state

#	Current State	Next State	Condition	Comment
1	`TX_DS_IDLE	`TX_DS_MAIN	[!(! pi_regs_csr15_st)]
2	`TX_DS_MAIN	`TX_DS_READ	[(tx_ds_allowed)]
3	`TX_DS_READ	`TX_DS_WAIT	[((pi_host_sdva) && (pi_host_sdata[31]))]
4	`TX_DS_READ	`TX_DS_SUSPEND	[((pi_host_sdva) && !(pi_host_sdata[31]))]
5	`TX_DS_WAIT	`TX_DS_MAIN	[(tx_valid_ds_read)]
6	`TX_DS_SUSPEND	`TX_DS_MAIN	[(pi_regs_csr0_ape && tx_ds_poll_cnt == pi_regs_csr0_tap || pi_regs_csr1_tpd)]

always @ ( posedge clock or negedge reset )

FSM Transitions for tx_state

#	Current State	Next State	Condition	Comment
1	`TX_IDLE	`TX_READ_DS	[(!(! pi_regs_csr15_st) && !(tx_ds_addr_valid && ! pi_tx_full && ! pi_tx_last_wr && ! tx_upd_fifo_full && ! tx_req) && (tx_allowed))]
2	`TX_READ_DS	`TX_READ_PAUSE	[((pi_host_sdva) && !(tx_burst_cnt == 0) && !(tx_burst_cnt == 1) && (tx_burst_cnt == 2))]
3	`TX_READ_PAUSE	`TX_IDLE	[(! tx_ds_valid)]
4	`TX_READ_PAUSE	`TX_READ	[(!(! tx_ds_valid) && !(! pi_tx_full && ! pi_tx_last_wr && ! tx_req) && (tx_allowed))]
5	`TX_READ	`TX_LW_FRM	[((pi_host_sdva) && (tx_mlast1) && (tx_word_cnt >= 16'h1000) && (pi_tx_last_wr)), ((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && (tx_ds1[30]) && (pi_tx_last_wr))]
6	`TX_READ	`TX_IDLE	[((pi_host_sdva) && (tx_mlast1) && (tx_word_cnt >= 16'h1000) && !(pi_tx_last_wr)), ((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && (tx_ds1[30]) && !(pi_tx_last_wr))]
7	`TX_READ	`TX_LW_DS	[((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && !(tx_ds1[30]) && (pi_tx_last_wr))]
8	`TX_READ	`TX_WRITE_DS	[((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && !(tx_ds1[30]) && !(pi_tx_last_wr))]
9	`TX_READ	`TX_LW_BUFF	[((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && !(tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && (pi_tx_last_wr))]
10	`TX_READ	`TX_READ_PAUSE	[((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && !(tx_buff_cnt == tx_curr_buff_size - 1) && (tx_burst_cnt == pi_config_burst_size - 1) && !(pi_tx_last_wr)), ((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && (tx_buff_cnt == tx_curr_buff_size - 1) && !(tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && !(pi_tx_last_wr))]
11	`TX_READ	`TX_LW_BURST	[((pi_host_sdva) && !(tx_mlast1) && (pi_tx_last_wr || pi_tx_full)), ((pi_host_sdva) && (tx_mlast1) && !(tx_word_cnt >= 16'h1000) && !(tx_buff_cnt == tx_curr_buff_size - 1) && (tx_burst_cnt == pi_config_burst_size - 1) && (pi_tx_last_wr))]
12	`TX_LW_FRM	`TX_IDLE	[!(pi_tx_last_wr)]
13	`TX_LW_DS	`TX_WRITE_DS	[!(pi_tx_last_wr)]
14	`TX_WRITE_DS	`TX_IDLE	[(pi_host_sdva)]
15	`TX_LW_BUFF	`TX_READ_PAUSE	[!(pi_tx_last_wr)]
16	`TX_LW_BURST	`TX_READ_PAUSE	[!(pi_tx_last_wr)]
17	default	`TX_IDLE	[EMPTY]	illegal state

always @ ( posedge clock or negedge reset )

tx_upd_fifo holds data tx_upd_fifo_wa holds write address tx_upd_fifo_ra holds read address tx_state process write and increments tx_upd_fifo_wa tx_update_ds process read and increments tx_upd_fifo_ra

always @ ( posedge clock or negedge reset )

this process reads from both tx_upd_fifo and tx_upd_resp_fifo, constructs TX_RDS0 and assert tx_ds_req to arbiter along with address(tx_upd_fifo) and data (tx_upd_resp_fifo)

FSM Transitions for tx_upd_state

#	Current State	Next State	Condition	Comment
1	`TX_DS_UPD_IDLE	`TX_DS_UPD_WRITE	[(tx_upd_req && tx_upd_allowed)]
2	`TX_DS_UPD_WRITE	`TX_DS_UPD_IDLE	[(pi_host_sdva)]

always @ ( posedge clock or negedge reset )

process for arbiter

always @ ( arb_state or rx_req or tx_req or rx_ds_req or tx_ds_req or tx_upd_req )

arbiter allowed calculation tx_frame_transmit

always @ ( arb_state or rx_allowed or tx_allowed or rx_ds_allowed or tx_ds_allowed or tx_upd_allowed )

arbiter next state calculation

FSM Transitions for arb_state

#	Current State	Next State	Condition	Comment
1	`ARB_IDLE	`ARB_S0	[(arb_enable)]

always @ ( rx_allowed or tx_allowed or rx_ds_allowed or tx_ds_allowed or tx_upd_allowed or rx_mcmd or rx_maddr or rx_mdata or rx_mlast or tx_mcmd or tx_maddr or tx_mdata or tx_mlast or rx_ds_mcmd or rx_ds_maddr or rx_ds_mlast or tx_ds_mcmd or tx_ds_maddr or tx_ds_mlast or tx_upd_mcmd or tx_upd_maddr or tx_upd_mdata or tx_upd_mlast )

arbiter multiplexor

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