Module ip_mac_rx_top_g

RX_MEM_ADDRpi_rx_resetlogicpi_host_resetlogicpi_host_hw_rstlogicpi_rx_f_clocklogicpi_rx_g_clock[2:0]logicpi_tx_gmii_vallogicpi_tx_gmii_errlogicpi_tx_gmii_data[7:0]logicpi_tx_xmit_nfclogicpi_rx_gmii_sellogicpi_gmii_vallogicpi_gmii_data[7:0]logicpi_gmii_errlogicpi_rx_gigabitlogicpi_rx_half_duplexlogicpi_rx_loopbacklogicpi_rx_fc_enablelogicpi_host_hash_nfixlogicpi_host_littlelogicpi_rx_hash_nfixlogicpi_rx_inverselogicpi_rx_multicastlogicpi_rx_pass_multilogicpi_rx_promisclogicpi_rx_pass_alllogicpi_rx_high_thrs[RX_MEM_ADDR:0]logicpi_rx_low_thrs[RX_MEM_ADDR:0]logicpi_host_wakeuplogicpi_host_wr_data[31:0]logicpi_host_wr_setuplogicpi_host_f_clocklogicpi_host_g_clocklogicpi_host_enable_rdlogicpi_host_stop_rcvlogicpo_rx_en_clocklogic[2:0]po_host_init_donelogicpo_rx_fc_tx_offlogicpo_rx_fc_xoff_tgllogicpo_rx_fc_xon_tgllogicpo_host_en_clocklogicpo_host_empty_rdlogicpo_host_last_rdlogicpo_host_data_rdlogic[31:0]po_host_byte_rdlogic[1:0]po_host_start_rdlogicpo_host_end_rdlogicpo_host_error_rdlogicpo_host_stop_rcvlogic

Block Diagram of ip_mac_rx_top_g

Parameters

Name

Default

Description

RX_MEM_ADDR

6

Receive memory address width (9 -> 512 locations, 10->1024)

Ports

Name

Type

Direction

Description

pi_rx_reset

wire logic

input

Global Software/Hardware Reset (receive clock domain)

pi_host_reset

wire logic

input

Global Software/Hardware Reset (host clock domain)

pi_host_hw_rst

wire logic

input

Global Hardware Reset (host clock domain)

pi_rx_f_clock

wire logic

input

Receive clock Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)

pi_rx_g_clock

wire logic [2 : 0]

input

Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)

po_rx_en_clock

wire logic [2 : 0]

output

Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)

po_host_init_done

wire logic

output

Initialisation done Receive initialisation done (host clock domain)

pi_tx_gmii_val

wire logic

input

Loopback GMII/MII Data Valid, Data Input Signals and Alignment Error Loopback MII/GMII data valid indication (from TX)

pi_tx_gmii_err

wire logic

input

Loopback MII/GMII error indication (from TX)

pi_tx_gmii_data

wire logic [7 : 0]

input

Loopback MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from TX)

pi_tx_xmit_nfc

wire logic

input

Transmit full duplex data frame transmit enable pending (non flow control frame is transmitted) Transmit FSM data frame transmit enable (transmit clock domain)

pi_rx_gmii_sel

wire logic

input

NOTE: This signal is not asserted during flow control frame transmission GMII/MII Data Valid, Data Input Signals and Alignment Error Receive GMII data select (demultiplex MII interface indication)

pi_gmii_val

wire logic

input

Note: po_rx_gmii_sel is balanced with the internal receive clock Receive MII/GMII data valid indication (from PHY)

pi_gmii_data

wire logic [7 : 0]

input

Receive MII/GMII error indication (from PHY)

pi_gmii_err

wire logic

input

Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY)

pi_rx_gigabit

wire logic

input

Operating 1000 Mbps (Gigabit) mode

pi_rx_half_duplex

wire logic

input

Operating Half Duplex mode

pi_rx_loopback

wire logic

input

Loopback mode select

pi_rx_fc_enable

wire logic

input

Receive flow control enable (flow control decoding enable)

po_rx_fc_tx_off

wire logic

output

Received FC packet (Transmit stop command)

po_rx_fc_xoff_tgl

wire logic

output

(to TX EMAC) insert XOFF flow control information

po_rx_fc_xon_tgl

wire logic

output

(to TX EMAC) insert XON flow control information

pi_host_hash_nfix

wire logic

input

Hash filtering + 1 Address match / 16 Address match

pi_host_little

wire logic

input

Little endian (data path organisation)

pi_rx_hash_nfix

wire logic

input

Configuration Filtering Hash/Exact Hash filtering + 1 Address match / 16 Address match

pi_rx_inverse

wire logic

input

Inverse match filtering mode

pi_rx_multicast

wire logic

input

When asserted the imperfect filtering refers only for multicast addressees

pi_rx_pass_multi

wire logic

input

Pass all multicast addresses

pi_rx_promisc

wire logic

input

Promiscuos Mode (no DA filter)

pi_rx_pass_all

wire logic

input

pass all bad frames (including FC frames)

pi_rx_high_thrs

wire logic [RX_MEM_ADDR : 0]

input

from configuration FC high threshold

pi_rx_low_thrs

wire logic [RX_MEM_ADDR : 0]

input

from configuration FC low threshold

pi_host_wakeup

wire logic

input

From/To Receive DMA (setup frame) Wake-up internal clock used by the Setup Frame FSM,

pi_host_wr_data

wire logic [31 : 0]

input

should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be deasserted 2 clock cycles after Setup Frame completition Setup Frame data (HOST clock synchronous)

pi_host_wr_setup

wire logic

input

Setup Frame write enable (HOST clock synchronous)

pi_host_f_clock

wire logic

input

Receive data path HOST interface Free HOST interface clock signal

pi_host_g_clock

wire logic

input

Gated Free HOST interface clock signal

po_host_en_clock

wire logic

output

Enable Free HOST interface clock signal

pi_host_enable_rd

wire logic

input

Receive MAC data path, HOST enable command

po_host_empty_rd

wire logic

output

Receive MAC data path, HOST FIFO empty indication

po_host_last_rd

wire logic

output

Receive MAC data path, HOST FIFO last location indication

po_host_data_rd

wire logic [31 : 0]

output

Receive MAC data path, HOST data (transmit data)

po_host_byte_rd

wire logic [1 : 0]

output

Receive MAC data path, HOST byte enable (transmit data byte enable)

po_host_start_rd

wire logic

output

Receive MAC data path, HOST start of frame indication

po_host_end_rd

wire logic

output

Receive MAC data path, HOST start of frame indication

po_host_error_rd

wire logic

output

Receive MAC data path, HOST frame error indication (asserted when

pi_host_stop_rcv

wire logic

input

frame is bigger than 64 bytes and receive MAC cannot drop the frame or pass bad frames mode is selected by asserting pi_emac_pass_all) Receive Start/Stop Receive MAC, receive stopped indication (HOST clock synchronous)

po_host_stop_rcv

wire logic

output

Receive MAC, receive stop command (HOST clock synchronous)

Instances

Submodules

cfg_hash (ip_mac_cfg_hash_g) pi_reset pi_f_clock pi_g_clock po_en_clock pi_wakeup pi_wr_data pi_wr_setup pi_hash_nfix pi_little po_wr_en po_wr_data po_wr_addr fc_dec (ip_mac_fc_dec_g) pi_reset pi_f_clock pi_g_clock po_en_clock pi_gigabit pi_xmit_nfc pi_fc_enable pi_fc_toggle pi_fc_value po_fc_tx_off rx_async (ip_async_fifo_g) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd pi_enable_wr pi_enable_rd po_full_wr po_empty_rd po_last_wr po_last_rd pi_data_wr po_data_rd rx_data_dram (ip_mac_dram_002) pi_clock_wr pi_clock_rd pi_addr_wr pi_addr_rd pi_wr_en pi_data_wr po_data_rd rx_dram_hash_0 (ip_mac_dram_004) pi_clock_wr pi_clock_rd pi_addr_wr pi_addr_rd pi_wr_en pi_data_wr po_data_rd rx_dram_hash_1 (ip_mac_dram_003) pi_clock_wr pi_clock_rd pi_addr_wr pi_addr_rd pi_wr_en pi_data_wr po_data_rd rx_endian (ip_mac_big_endian) pi_little pi_data po_data rx_fifo (ip_mac_rx_fifo_g) pi_reset pi_f_clock pi_full_wr pi_last_wr po_enable_wr pi_wr_ptr pi_wr_addr po_rd_addr pi_wr_sof pi_wr_en pi_high_thrs pi_low_thrs po_fc_xoff_tgl po_fc_xon_tgl rx_gmii (ip_mac_rx_gmii_g) pi_loopback pi_tx_gmii_val pi_tx_gmii_err pi_tx_gmii_data pi_gmii_val pi_gmii_data pi_gmii_err po_gmii_val po_gmii_data po_gmii_err rx_hash (ip_mac_rx_hash_g) pi_reset pi_f_clock pi_g_clock po_en_clock pi_hash_addr pi_dest_addr pi_new_match pi_abort pi_hash_nfix pi_inverse pi_multicast pi_pass_multi pi_promisc pi_pass_all pi_rd_data po_rd_addr po_err_match po_match po_fc_match rx_state (ip_mac_rx_state_g) pi_reset pi_f_clock pi_g_clock po_en_clock pi_gmii_val pi_gmii_data pi_gmii_err pi_gigabit pi_half_duplex pi_loopback pi_little po_fc_toggle po_fc_value po_start po_end po_error po_byte po_data pi_rd_addr po_wr_addr po_wr_ptr po_push pi_err_match pi_match pi_fc_match pi_pass_all po_hash_addr po_dest_addr po_new_match po_abort pi_stop_rcv po_stop_rcv rx_sync (ip_mac_rx_sync_g) pi_rx_reset pi_rx_f_clock po_host_idone pi_host_reset pi_host_f_clock pi_rx_stop po_host_stop pi_host_stop po_rx_stop pi_tx_xmit_nfc po_rx_xmit_nfc host_data_rd {po_host_start_rd, po_host_end_rd, po_host_error_rd, po_host_byte_rd, host_data_rd} po_host_byte_rd po_host_error_rd po_host_end_rd po_host_start_rd {rx_mac_wr_start, rx_mac_wr_end, rx_mac_wr_error, rx_mac_wr_byte, rx_mac_wr_data} rx_mac_wr_data rx_mac_wr_byte rx_mac_wr_error rx_mac_wr_end rx_mac_wr_start mac_rx_top (ip_mac_rx_top_g) pi_rx_reset pi_host_reset pi_host_hw_rst pi_rx_f_clock pi_rx_g_clock po_rx_en_clock po_host_init_done pi_tx_gmii_val pi_tx_gmii_err pi_tx_gmii_data pi_tx_xmit_nfc pi_rx_gmii_sel pi_gmii_val pi_gmii_data pi_gmii_err pi_rx_gigabit pi_rx_half_duplex pi_rx_loopback pi_rx_fc_enable po_rx_fc_tx_off po_rx_fc_xoff_tgl po_rx_fc_xon_tgl pi_host_hash_nfix pi_host_little pi_rx_hash_nfix pi_rx_inverse pi_rx_multicast pi_rx_pass_multi pi_rx_promisc pi_rx_pass_all pi_rx_high_thrs pi_rx_low_thrs pi_host_wakeup pi_host_wr_data pi_host_wr_setup pi_host_f_clock pi_host_g_clock po_host_en_clock pi_host_enable_rd po_host_empty_rd po_host_last_rd po_host_data_rd po_host_byte_rd po_host_start_rd po_host_end_rd po_host_error_rd pi_host_stop_rcv po_host_stop_rcv

Schematic Diagram of ip_mac_rx_top_g