Module ip_mac_rx_top_g

ip_mac_rx_top_g #( .RX_MEM_ADDR(RX_MEM_ADDR) ) u_ip_mac_rx_top_g ( .pi_rx_reset(pi_rx_reset), .pi_host_reset(pi_host_reset), .pi_host_hw_rst(pi_host_hw_rst), .pi_rx_f_clock(pi_rx_f_clock), .pi_rx_g_clock(pi_rx_g_clock), .po_rx_en_clock(po_rx_en_clock), .po_host_init_done(po_host_init_done), .pi_tx_gmii_val(pi_tx_gmii_val), .pi_tx_gmii_err(pi_tx_gmii_err), .pi_tx_gmii_data(pi_tx_gmii_data), .pi_tx_xmit_nfc(pi_tx_xmit_nfc), .pi_rx_gmii_sel(pi_rx_gmii_sel), .pi_gmii_val(pi_gmii_val), .pi_gmii_data(pi_gmii_data), .pi_gmii_err(pi_gmii_err), .pi_rx_gigabit(pi_rx_gigabit), .pi_rx_half_duplex(pi_rx_half_duplex), .pi_rx_loopback(pi_rx_loopback), .pi_rx_fc_enable(pi_rx_fc_enable), .po_rx_fc_tx_off(po_rx_fc_tx_off), .po_rx_fc_xoff_tgl(po_rx_fc_xoff_tgl), .po_rx_fc_xon_tgl(po_rx_fc_xon_tgl), .pi_host_hash_nfix(pi_host_hash_nfix), .pi_host_little(pi_host_little), .pi_rx_hash_nfix(pi_rx_hash_nfix), .pi_rx_inverse(pi_rx_inverse), .pi_rx_multicast(pi_rx_multicast), .pi_rx_pass_multi(pi_rx_pass_multi), .pi_rx_promisc(pi_rx_promisc), .pi_rx_pass_all(pi_rx_pass_all), .pi_rx_high_thrs(pi_rx_high_thrs), .pi_rx_low_thrs(pi_rx_low_thrs), .pi_host_wakeup(pi_host_wakeup), .pi_host_wr_data(pi_host_wr_data), .pi_host_wr_setup(pi_host_wr_setup), .pi_host_f_clock(pi_host_f_clock), .pi_host_g_clock(pi_host_g_clock), .po_host_en_clock(po_host_en_clock), .pi_host_enable_rd(pi_host_enable_rd), .po_host_empty_rd(po_host_empty_rd), .po_host_last_rd(po_host_last_rd), .po_host_data_rd(po_host_data_rd), .po_host_byte_rd(po_host_byte_rd), .po_host_start_rd(po_host_start_rd), .po_host_end_rd(po_host_end_rd), .po_host_error_rd(po_host_error_rd), .pi_host_stop_rcv(pi_host_stop_rcv), .po_host_stop_rcv(po_host_stop_rcv) );

Block Diagram of ip_mac_rx_top_g

Parameters

Name	Default	Description
RX_MEM_ADDR	6	Receive memory address width (9 -> 512 locations, 10->1024)

Ports

Name	Type	Direction	Description
pi_rx_reset	wire logic	input	Global Software/Hardware Reset (receive clock domain)
pi_host_reset	wire logic	input	Global Software/Hardware Reset (host clock domain)
pi_host_hw_rst	wire logic	input	Global Hardware Reset (host clock domain)
pi_rx_f_clock	wire logic	input	Receive clock Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_rx_g_clock	wire logic [2 : 0]	input	Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_rx_en_clock	wire logic [2 : 0]	output	Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_host_init_done	wire logic	output	Initialisation done Receive initialisation done (host clock domain)
pi_tx_gmii_val	wire logic	input	Loopback GMII/MII Data Valid, Data Input Signals and Alignment Error Loopback MII/GMII data valid indication (from TX)
pi_tx_gmii_err	wire logic	input	Loopback MII/GMII error indication (from TX)
pi_tx_gmii_data	wire logic [7 : 0]	input	Loopback MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from TX)
pi_tx_xmit_nfc	wire logic	input	Transmit full duplex data frame transmit enable pending (non flow control frame is transmitted) Transmit FSM data frame transmit enable (transmit clock domain)
pi_rx_gmii_sel	wire logic	input	NOTE: This signal is not asserted during flow control frame transmission GMII/MII Data Valid, Data Input Signals and Alignment Error Receive GMII data select (demultiplex MII interface indication)
pi_gmii_val	wire logic	input	Note: po_rx_gmii_sel is balanced with the internal receive clock Receive MII/GMII data valid indication (from PHY)
pi_gmii_data	wire logic [7 : 0]	input	Receive MII/GMII error indication (from PHY)
pi_gmii_err	wire logic	input	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY)
pi_rx_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_rx_half_duplex	wire logic	input	Operating Half Duplex mode
pi_rx_loopback	wire logic	input	Loopback mode select
pi_rx_fc_enable	wire logic	input	Receive flow control enable (flow control decoding enable)
po_rx_fc_tx_off	wire logic	output	Received FC packet (Transmit stop command)
po_rx_fc_xoff_tgl	wire logic	output	(to TX EMAC) insert XOFF flow control information
po_rx_fc_xon_tgl	wire logic	output	(to TX EMAC) insert XON flow control information
pi_host_hash_nfix	wire logic	input	Hash filtering + 1 Address match / 16 Address match
pi_host_little	wire logic	input	Little endian (data path organisation)
pi_rx_hash_nfix	wire logic	input	Configuration Filtering Hash/Exact Hash filtering + 1 Address match / 16 Address match
pi_rx_inverse	wire logic	input	Inverse match filtering mode
pi_rx_multicast	wire logic	input	When asserted the imperfect filtering refers only for multicast addressees
pi_rx_pass_multi	wire logic	input	Pass all multicast addresses
pi_rx_promisc	wire logic	input	Promiscuos Mode (no DA filter)
pi_rx_pass_all	wire logic	input	pass all bad frames (including FC frames)
pi_rx_high_thrs	wire logic [RX_MEM_ADDR : 0]	input	from configuration FC high threshold
pi_rx_low_thrs	wire logic [RX_MEM_ADDR : 0]	input	from configuration FC low threshold
pi_host_wakeup	wire logic	input	From/To Receive DMA (setup frame) Wake-up internal clock used by the Setup Frame FSM,
pi_host_wr_data	wire logic [31 : 0]	input	should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be deasserted 2 clock cycles after Setup Frame completition Setup Frame data (HOST clock synchronous)
pi_host_wr_setup	wire logic	input	Setup Frame write enable (HOST clock synchronous)
pi_host_f_clock	wire logic	input	Receive data path HOST interface Free HOST interface clock signal
pi_host_g_clock	wire logic	input	Gated Free HOST interface clock signal
po_host_en_clock	wire logic	output	Enable Free HOST interface clock signal
pi_host_enable_rd	wire logic	input	Receive MAC data path, HOST enable command
po_host_empty_rd	wire logic	output	Receive MAC data path, HOST FIFO empty indication
po_host_last_rd	wire logic	output	Receive MAC data path, HOST FIFO last location indication
po_host_data_rd	wire logic [31 : 0]	output	Receive MAC data path, HOST data (transmit data)
po_host_byte_rd	wire logic [1 : 0]	output	Receive MAC data path, HOST byte enable (transmit data byte enable)
po_host_start_rd	wire logic	output	Receive MAC data path, HOST start of frame indication
po_host_end_rd	wire logic	output	Receive MAC data path, HOST start of frame indication
po_host_error_rd	wire logic	output	Receive MAC data path, HOST frame error indication (asserted when
pi_host_stop_rcv	wire logic	input	frame is bigger than 64 bytes and receive MAC cannot drop the frame or pass bad frames mode is selected by asserting pi_emac_pass_all) Receive Start/Stop Receive MAC, receive stopped indication (HOST clock synchronous)
po_host_stop_rcv	wire logic	output	Receive MAC, receive stop command (HOST clock synchronous)

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g #(.RX_MEM_ADDR(10))

Submodules

• ip_mac_rx_top_g #(.RX_MEM_ADDR(10))

  • cfg_hash : ip_mac_cfg_hash_g

  • fc_dec : ip_mac_fc_dec_g

  • rx_async : ip_async_fifo_g #(.MEM_WIDTH(37))

  • rx_data_dram : ip_mac_dram_002 #(.MEM_ADDR(10), .MEM_WIDTH(37))

  • rx_dram_hash_0 : ip_mac_dram_004 #(.MEM_ADDR(4), .MEM_WIDTH(32))

  • rx_dram_hash_1 : ip_mac_dram_003 #(.MEM_ADDR(4), .MEM_WIDTH(16))

  • rx_endian : ip_mac_big_endian

  • rx_fifo : ip_mac_rx_fifo_g #(.MEM_ADDR(10))

  • rx_gmii : ip_mac_rx_gmii_g

  • rx_hash : ip_mac_rx_hash_g

  • rx_state : ip_mac_rx_state_g #(.MEM_ADDR(10))

  • rx_sync : ip_mac_rx_sync_g

Schematic Diagram of ip_mac_rx_top_g

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