Module ip_sync_reset_g
Block Diagram of ip_sync_reset_g
Name |
Type |
Direction |
Description |
|---|---|---|---|
pi_reset |
wire logic |
input |
Asynchronous reset |
pi_clock |
wire logic |
input |
Input clock |
pi_test_en |
wire logic |
input |
Test enable (multiplex information) |
po_reset |
wire logic |
output |
Synchronous reset (functional clock balanced) |
Always Blocks
- always @ ( posedge pi_clock or negedge pi_reset )
Metastable Reset Synchronization
Instances
- ip_emac_top : ip_emac_top
- host_clk_mng : ip_host_clk_mng_g
host_sreset : ip_sync_reset_g
hw_host_sreset : ip_sync_reset_g
- mac_top : ip_mac_top_g
- mac_clk_mng : ip_mac_clk_mng_g
host_sreset : ip_sync_reset_g
hw_host_sreset : ip_sync_reset_g
mdio_sreset : ip_sync_reset_g
rx_sreset : ip_sync_reset_g
tx_sreset : ip_sync_reset_g
×
Synchronous resets are used in designs to safely reset the DFFs from one clock domain. The asynchronous reset can generate an unstable condition in design due to the metastability when reset is removed, if the DFF input data is different than the reset value output DFF data (for example a free counter)