Module ip_mac_dram_001

ip_mac_dram_001 #( .MEM_ADDR(MEM_ADDR), .MEM_WIDTH(MEM_WIDTH) ) u_ip_mac_dram_001 ( .pi_clock_wr(pi_clock_wr), .pi_clock_rd(pi_clock_rd), .pi_addr_wr(pi_addr_wr), .pi_addr_rd(pi_addr_rd), .pi_wr_en(pi_wr_en), .pi_data_wr(pi_data_wr), .po_data_rd(po_data_rd) );

Block Diagram of ip_mac_dram_001

The internal DRAM memory modules have the property that when the read address selects a memory location, this location is write protected (locked for write operation). Since when FIFO is empty both read and write addresses points to the same address and the a write operation should be performed, the read memory address should point to an unused memory location in order to unlock the write operation. Moving the internal address to an unused location when write enable modifies the read operation timing since the read DRAM address does not point to the right read address. In order to avoid the timing read response delay a bypass register between input and output data is used. When FIFO is empty the output data reads the bypass register instead of DRAM memory output.

Note: No bypass is necessary for Hash table memory since the read is not performed in the same time memory is writed. Bypass data register and bypass select multiplexer is removed from this module

Parameters

Name	Default	Description
MEM_ADDR	9	Address width (9 -> 512 locations, 10->1024)
MEM_WIDTH	39	Data width

Ports

Name	Type	Direction	Description
pi_clock_wr	wire logic	input	Input write clock (multiplexed with scan clock ouside this module)
pi_clock_rd	wire logic	input	Input read clock
pi_addr_wr	wire logic [MEM_ADDR - 1 : 0]	input	Write address
pi_addr_rd	wire logic [MEM_ADDR - 1 : 0]	input	Read address
pi_wr_en	wire logic	input	Write enable
pi_data_wr	wire logic [MEM_WIDTH - 1 : 0]	input	Write data
po_data_rd	wire logic [MEM_WIDTH - 1 : 0]	output	Read data

Always Blocks

always @ ( pi_wr_en or pi_addr_rd or pi_addr_wr )

Read Pointer Move (when read pointer equal write pointer and write enable the read memory address should not point to the writed location)

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_tx_top : ip_mac_tx_top_g

      • tx_data_dram : ip_mac_dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(39))

Submodules

• ip_mac_dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(39))

  • dram_001 : dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(39))

Schematic Diagram of ip_mac_dram_001

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