Module ip_mac_rx_fifo_g

ip_mac_rx_fifo_g #( .MEM_ADDR(MEM_ADDR) ) u_ip_mac_rx_fifo_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_full_wr(pi_full_wr), .pi_last_wr(pi_last_wr), .po_enable_wr(po_enable_wr), .pi_wr_ptr(pi_wr_ptr), .pi_wr_addr(pi_wr_addr), .po_rd_addr(po_rd_addr), .pi_wr_sof(pi_wr_sof), .pi_wr_en(pi_wr_en), .pi_high_thrs(pi_high_thrs), .pi_low_thrs(pi_low_thrs), .po_fc_xoff_tgl(po_fc_xoff_tgl), .po_fc_xon_tgl(po_fc_xon_tgl) );

Block Diagram of ip_mac_rx_fifo_g

The EMAC Receive FIFO Control module is responsible to generate all the control signals necessary to transfer the data form the EMAC Receive Memory module to the EMAC Asynchronous FIFO module. The EMAC Receive FIFO Control module provides the memory write memory pointer and the write address, used by the EMAC Receive module in order to calculate if the memory is ready (actual frame transmission begins after the internal Receive memory had reached either a programmable threshold or after a full frame is contained in the memory). The write address is updated (takes the write pointer value) whenever the memory contains enough data for Receive. The pointer update is made when the number of words of the frame exceeds a programmed threshold value or the entire frame is in the memory.

Parameters

Name	Default	Description
MEM_ADDR	6	Transmit memory address width (9 -> 512 locations, 10->1024)

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Hardware/Software reset (active low)
pi_f_clock	wire logic	input	Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_full_wr	wire logic	input	Signals from/to Asynchronous FIFO Asynchronous FIFO full (no write can be performed)
pi_last_wr	wire logic	input	Asynchronous FIFO last valid location
po_enable_wr	reg	output	Asynchronous FIFO write enable
pi_wr_ptr	wire logic [MEM_ADDR : 0]	input	Signals from MAC State Machine Used by RX FIFO to compute the memory state (full/empty/ready)
pi_wr_addr	wire logic [MEM_ADDR : 0]	input	Write address (memory write address)
po_rd_addr	reg [MEM_ADDR : 0]	output	Used by EMAC Receive State to see the momory state (full/empty/ready)
pi_wr_sof	wire logic	input	Memory SOF and write enable (use for fc toggle function) Start of frame indication (resend a new FC packet since
pi_wr_en	wire logic	input	a new frame was received during pause period, a previously FC was send) FIFO write enable (valid start of frame)
pi_high_thrs	wire logic [MEM_ADDR : 0]	input	Flow control From configuration FC high threshold
pi_low_thrs	wire logic [MEM_ADDR : 0]	input	From configuration FC low threshold
po_fc_xoff_tgl	reg	output	(to TX EMAC) insert XOFF flow control information
po_fc_xon_tgl	reg	output	(to TX EMAC) insert XON flow control information

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset )

Low/High Threshold Assignment

FSM Transitions for high_low_en

#	Current State	Next State	Condition	Comment
1	1'b1	1'b0	[(!(~ pi_reset) && !(pi_high_thrs < fifo_level && pi_wr_en == 1'b1 && pi_wr_sof == 1'b1))]

always @ ( posedge pi_f_clock or negedge pi_reset )

Number of full locations

always @ ( po_rd_addr or pi_wr_ptr or po_enable_wr or read_inc )

Assign FIFO empty (move memory address when empty)

always @ ( posedge pi_f_clock or negedge pi_reset )

Write Enable & Address/Pointer Update Process

FSM Transitions for po_enable_wr

#	Current State	Next State	Condition	Comment
1	1'b1	1'b0	[(!(~ pi_reset) && !(valid_data == 1'b0) && !(pi_full_wr == 1'b1))]

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • rx_fifo : ip_mac_rx_fifo_g #(.MEM_ADDR(10))

×