Module ip_mac_hostif_tx

Block Diagram of ip_mac_hostif_tx

Ports
Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous pi_reset
pi_g_clock	wire logic	input	host gated clock
pi_g1_clock	wire logic	input	host gated clock 1
pi_f_clock	wire logic	input	host free clock
po_en_clock	reg	output	enable clock condition
po_en1_clock	reg	output	enable clock condition 1
po_tx_enable_wr	wire logic	output	tx mac fifo interface rx fifo read command
pi_tx_full	wire logic	input	rx fifo full
pi_tx_last_wr	wire logic	input	rx fifo almost full
po_tx_data	wire logic [31 : 0]	output	rx fifo data
po_tx_be	wire logic [1 : 0]	output	tx fifo data byte enable
po_tx_sof	wire logic	output	tx fifo start of frame
po_tx_eof	wire logic	output	tx fifo end of frame
po_tx_put_crc	wire logic	output	put crc indication (valid only when sof=1)
po_tx_put_padding	wire logic	output	put padding indication (valid only when sof=1)
po_tx_err	wire logic	output	put error indication (valid only when eof=1)
pi_host_sdata	wire logic [31 : 0]	input	host interface from host interface
pi_host_sdva	wire logic	input	from host interface
po_tx_upd_read	wire logic	output	TX update fifo interface
pi_tx_upd_empty	wire logic	input
pi_tx_upd_last	wire logic	input
pi_tx_upd_data	wire logic [9 : 0]	input
tx_valid_ds_read	reg	output	ip_mac_hostif_txds to ip_mac_hostif_txds (new descriptor polling enabled)
tx_ds_next_addr	wire logic [31 : 0]	input	from ip_mac_hostif_txds (new descriptor address)
tx_ds_addr_valid	wire logic	input	from ip_mac_hostif_txds (new descriptor address valid)
pi_tx_ds0_poll	wire logic [31 : 0]	input	from ip_mac_hostif_txds (new descriptor address valid)
po_tx_ds1	wire logic [1 : 0]	output
po_tx_ds3	wire logic [31 : 0]	output
tx_allowed	wire logic	input	ip_mac_hostif_arb from pi_mac_hostif_arb (tx upd req allowed)
tx_req	reg	output	request to arb from tx upd ds process
tx_mcmd	reg [1 : 0]	output	tx update ds mcmd
tx_maddr	reg [31 : 0]	output	tx update ds maddr
tx_mlast	wire logic	output	tx update ds mlast
tx_frame_transmit	reg	output	to ip_mac_hostif_arb (used in arbitration process)
tx_upd_allowed	wire logic	input	from pi_mac_hostif_arb (tx upd req allowed)
tx_upd_req	reg	output	request to arb from tx upd ds process
tx_upd_mcmd	reg [1 : 0]	output	tx update ds mcmd
tx_upd_maddr	reg [31 : 0]	output	tx update ds maddr
tx_upd_mdata	reg [31 : 0]	output	tx update ds mdata
tx_upd_mlast	reg	output	tx update ds mlast
po_regs_csr5_unf	reg	output	ip_mac_regs_bank (config) transmit underflow
po_regs_csr5_ti	reg	output	transmit frame complete (to CSR5 TI)
po_regs_csr5_tjt	reg	output	transmit jabber timeout error
pi_regs_csr14_st	wire logic	input	start/stop transmit
pi_config_burst_size	wire logic [5 : 0]	input	limit for rx tx burst transfer

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset ) : state machine for tx descriptor based transfer

always @ ( posedge pi_g1_clock or negedge pi_reset ) : tx_upd_fifo holds data tx_upd_fifo_wa holds write address tx_upd_fifo_ra holds read address tx_state process write and increments tx_upd_fifo_wa tx_update_ds process read and increments tx_upd_fifo_ra

always @ ( posedge pi_g1_clock or negedge pi_reset ) : this process reads from both tx_upd_fifo and tx_upd_resp_fifo, constructs TX_RDS0 and assert tx_ds_req to arbiter along with address(tx_upd_fifo) and data (tx_upd_resp_fifo)

FSM Transitions for tx_upd_state
#	Current State	Next State	Condition	Comment
1	`TX_DS_UPD_IDLE	`TX_DS_UPD_WRITE	[(!(~ pi_reset) && (tx_upd_req && tx_upd_allowed))]
2	`TX_DS_UPD_WRITE	`TX_DS_UPD_IDLE	[(!(~ pi_reset) && (pi_host_sdva))]

always @ ( posedge pi_f_clock or negedge pi_reset ) 

FSM Transitions for tx_state
#	Current State	Next State	Condition	Comment
1	`TX_IDLE	`TX_READ_DS	[(!(~ pi_reset) && !(! pi_regs_csr14_st \|\| ! tx_ds_addr_valid) && !(tx_ds_addr_valid && ! pi_tx_full && ! pi_tx_last_wr && ! tx_upd_fifo_full && ! tx_req) && (tx_allowed))]
2	`TX_READ_DS	`TX_READ_PAUSE	[(!(~ pi_reset) && (pi_host_sdva) && !(tx_burst_cnt == 0) && !(tx_burst_cnt == 1) && (tx_burst_cnt == 2))]
3	`TX_READ_PAUSE	`TX_IDLE	[(!(~ pi_reset) && (! tx_ds_valid))]
4	`TX_READ_PAUSE	`TX_READ	[(!(~ pi_reset) && !(! tx_ds_valid) && !(! pi_tx_full && ! pi_tx_last_wr && ! tx_req) && (tx_allowed))]
5	`TX_READ	`TX_WRITE_DS	[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && (tx_next_state == 4'b0100)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff \|\| tx_ds1[24] \|\| tx_ds1[21 : 11] == 0) && !(tx_ds1[30]) && !(tx_word_remained))]
6	`TX_READ	`TX_IDLE	[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && !(tx_next_state == 4'b0100) && (tx_next_state == 4'b0000)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff \|\| tx_ds1[24] \|\| tx_ds1[21 : 11] == 0) && (tx_ds1[30]) && !(tx_word_remained))]
7	`TX_READ	`TX_READ_PAUSE	[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && !(tx_next_state == 4'b0100) && !(tx_next_state == 4'b0000)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && !(tx_buff_cnt == tx_curr_buff_size - 1) && (tx_burst_cnt == pi_config_burst_size - 1) && !(tx_word_remained)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && !(tx_cur_buff \|\| tx_ds1[24] \|\| tx_ds1[21 : 11] == 0) && !(tx_word_remained))]
8	`TX_WRITE_DS	`TX_IDLE	[(!(~ pi_reset) && (tx_allowed && pi_host_sdva))]
9	default	`TX_IDLE	[!(~ pi_reset)]	illegal state

Instances

ip_emac_top : ip_emac_top
- host_if : ip_mac_hostif_top
  
  hostif_tx : ip_mac_hostif_tx