Module ip_mac_regs_bank

pi_host_resetlogicpi_host_clocklogicpi_config_mcmd[1:0]logicpi_config_maddr[31:0]logicpi_config_mdata[31:0]logicpi_host_serrlogicpi_host_base_addr[23:0]logicpi_rx_ovflogicpi_rx_csr5_rwtlogicpi_host_csr5_rpslogicpi_host_csr5_rulogicpi_host_csr5_rilogicpi_tx_csr5_unflogicpi_tx_csr5_tjtlogicpi_host_csr5_tulogicpi_host_csr5_tpslogicpi_host_csr5_tilogicpi_mdio_csr12_sblogicpi_mdio_csr13_merlogicpi_mdio_csr13_md[15:0]logicpi_tx_idonelogicpi_rx_idonelogicpo_config_sdvaregpo_config_sdatareg[31:0]po_config_serrregpo_host_intregpo_setup_wakeupregpo_setup_wr_datalogic[31:0]po_setup_wr_setuplogicpo_host_csr0_taplogic[15:0]po_host_csr0_apelogicpo_host_csr0_pbllogic[5:0]po_host_csr0_blelogicpo_host_csr0_dsologic[4:0]po_host_csr0_barlogicpo_host_csr14_swrlogicpo_host_csr1_tpdregpo_host_csr2_rpdregpo_host_csr3_stllogic[29:0]po_host_csr4_srllogic[29:0]po_tx_csr6_sflogicpo_tx_csr6_trlogic[10:0]po_global_csr6_omlogic[1:0]po_global_csr6_fdlogicpo_global_csr6_belogicpo_rx_csr6_pmlogicpo_rx_csr6_prlogicpo_rx_csr6_perfectflogicpo_rx_csr6_hashflogicpo_rx_csr6_inverseflogicpo_rx_csr6_multicast_onlylogicpo_rx_csr6_pblogicpo_mac_csr6_lblogicpo_tx_csr8_ifg1logic[7:0]po_tx_csr8_ifg2logic[7:0]po_tx_csr9_bllogic[15:0]po_tx_csr10_xonlogic[15:0]po_tx_csr10_xofflogic[15:0]po_rx_csr11_bcnlogic[5:0]po_rx_csr11_erfclogicpo_rx_csr11_etfclogicpo_rx_csr11_putlogic[10:0]po_rx_csr11_pltlogic[10:0]po_mdio_csr12_sblogicpo_mdio_csr12_rnwlogicpo_mdio_csr12_radlogic[4:0]po_mdio_csr12_dadlogic[4:0]po_mdio_csr13_mdlogic[15:0]po_host_csr14_srlogicpo_host_csr14_stlogicpo_tx_csr14_not_stlogicpo_tx_csr14_not_srlogicpo_global_cfda_slmlogicpo_global_cfda_szmlogic

Block Diagram of ip_mac_regs_bank

Ports

Name

Type

Direction

Description
pi_host_reset

wire logic

input

general interface host domain reset
pi_host_clock

wire logic

input

host domain clock
pi_config_mcmd

wire logic [1 : 0]

input

host access interface
pi_config_maddr

wire logic [31 : 0]

input
pi_config_mdata

wire logic [31 : 0]

input
po_config_sdva

reg

output

pi_config_mlast,
po_config_sdata

reg [31 : 0]

output
po_config_serr

reg

output
pi_host_serr

wire logic

input

failure on host data interface
pi_host_base_addr

wire logic [23 : 0]

input

internal space base address
po_host_int

reg

output

general interrupt to the host
po_setup_wakeup

reg

output

setup interface
po_setup_wr_data

wire logic [31 : 0]

output
po_setup_wr_setup

wire logic

output
po_host_csr0_tap

wire logic [15 : 0]

output

host domain register outputs & inputs
po_host_csr0_ape

wire logic

output
po_host_csr0_pbl

wire logic [5 : 0]

output
po_host_csr0_ble

wire logic

output
po_host_csr0_dso

wire logic [4 : 0]

output
po_host_csr0_bar

wire logic

output
po_host_csr14_swr

wire logic

output
po_host_csr1_tpd

reg

output

transmit poll demand
po_host_csr2_rpd

reg

output

receive poll demand
po_host_csr3_stl

wire logic [29 : 0]

output

transmit descriptor base address
po_host_csr4_srl

wire logic [29 : 0]

output

receive descriptor base address
pi_rx_ovf

wire logic

input

reveive overflow (from HOST If Rx statistic compilation)
pi_rx_csr5_rwt

wire logic

input

pi_host_csr5_ts, //transmit process state pi_host_csr5_rs, //receive process state receive watchdog timeout(16k limit)
pi_host_csr5_rps

wire logic

input

receive process stopped
pi_host_csr5_ru

wire logic

input

receive buffer unavailable
pi_host_csr5_ri

wire logic

input

receive interupt
pi_tx_csr5_unf

wire logic

input

transmit underflow (from HOST If Tx statistic compilation)
pi_tx_csr5_tjt

wire logic

input

transmit jabber time-out
pi_host_csr5_tu

wire logic

input

transmit buffer unavailable
pi_host_csr5_tps

wire logic

input

transmit process stopped
pi_host_csr5_ti

wire logic

input

transmit interrupt
po_tx_csr6_sf

wire logic

output

transmission store and forward OR transmit when threshold csr6[24:14] reached
po_tx_csr6_tr

wire logic [10 : 0]

output

transmission threshold
po_global_csr6_om

wire logic [1 : 0]

output

global operating mode (10/100/1G)
po_global_csr6_fd

wire logic

output

full-duplex mode enable
po_global_csr6_be

wire logic

output

burst enable (when 1G mode selected)
po_rx_csr6_pm

wire logic

output

receive pass all multicast enable
po_rx_csr6_pr

wire logic

output

receive promiscuous mode enable
po_rx_csr6_perfectf

wire logic

output

perfect filtering
po_rx_csr6_hashf

wire logic

output

hash filtering
po_rx_csr6_inversef

wire logic

output

inverse filtering
po_rx_csr6_multicast_only

wire logic

output

imperfect filtering
po_rx_csr6_pb

wire logic

output

receive pass bad frames
po_mac_csr6_lb

wire logic

output

loopback mode enable
po_tx_csr8_ifg1

wire logic [7 : 0]

output

pi_rx_csr8_mfc_inc, // missed frame counter increment command IFG1
po_tx_csr8_ifg2

wire logic [7 : 0]

output

IFG2
po_tx_csr9_bl

wire logic [15 : 0]

output

burst length
po_tx_csr10_xon

wire logic [15 : 0]

output

tx pause xon
po_tx_csr10_xoff

wire logic [15 : 0]

output

tx pause xoff
po_rx_csr11_bcn

wire logic [5 : 0]

output

receive backpressure collision number
po_rx_csr11_erfc

wire logic

output

receive enable flow control
po_rx_csr11_etfc

wire logic

output

transmit enable flow control
po_rx_csr11_put

wire logic [10 : 0]

output

pause upper threshold
po_rx_csr11_plt

wire logic [10 : 0]

output

pause lower threshold
po_mdio_csr12_sb

wire logic

output

MDIO start
pi_mdio_csr12_sb

wire logic

input

mdio busy
po_mdio_csr12_rnw

wire logic

output

MDIO r/w
po_mdio_csr12_rad

wire logic [4 : 0]

output

MDIO register address
po_mdio_csr12_dad

wire logic [4 : 0]

output

MDIO device address
pi_mdio_csr13_mer

wire logic

input

mdio error
po_mdio_csr13_md

wire logic [15 : 0]

output

MDIO write data to MDIO if
pi_mdio_csr13_md

wire logic [15 : 0]

input

MDIO read data from MDIO if
po_host_csr14_sr

wire logic

output

start / stop receive
po_host_csr14_st

wire logic

output

start / stop transmit
po_tx_csr14_not_st

wire logic

output

tx stop transmit
po_tx_csr14_not_sr

wire logic

output

rx stop receive
pi_tx_idone

wire logic

input

MAC tx initialization done
pi_rx_idone

wire logic

input

MAC rx initialization done
po_global_cfda_slm

wire logic

output

sleep mode enable
po_global_cfda_szm

wire logic

output

snooze mode enable

Always Blocks

always @ ( negedge pi_host_reset or posedge pi_host_clock )

R/W registers

`REGS_IDLE `REGS_IDLE = 3'b000 `REGS_HWRITE `REGS_HWRITE = 3'b100 `REGS_READ `REGS_READ = 3'b010 `REGS_WRITE `REGS_WRITE = 3'b001 DEFAULT default 2 [(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h48))] 3 [(!(~ pi_host_reset) && (device_selected) && !(pi_config_mcmd == 2'b01) && (pi_config_mcmd == 2'b10))] 1 [(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h00)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h04)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h08)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h0c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h10)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h14)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h18)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h1c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h20)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h24)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h28)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h2c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h30)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h34)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h38)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h3c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h40)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h44))] 5 [(!(~ pi_host_reset) && (hash_cnt == 1))] 6 [!(~ pi_host_reset)] 4 [!(~ pi_host_reset)] 7 [!(~ pi_host_reset)]
FSM Transitions for config_state

#

Current State

Next State

Condition

Comment

1

`REGS_IDLE

`REGS_WRITE

[(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h00)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h04)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h08)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h0c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h10)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h14)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h18)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h1c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h20)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h24)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h28)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h2c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h30)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h34)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h38)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h3c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h40)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h44))]

2

`REGS_IDLE

`REGS_HWRITE

[(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2'b01) && (rw_addr == 7'h48))]

3

`REGS_IDLE

`REGS_READ

[(!(~ pi_host_reset) && (device_selected) && !(pi_config_mcmd == 2'b01) && (pi_config_mcmd == 2'b10))]

4

`REGS_WRITE

`REGS_IDLE

[!(~ pi_host_reset)]

5

`REGS_HWRITE

`REGS_WRITE

[(!(~ pi_host_reset) && (hash_cnt == 1))]

6

`REGS_READ

`REGS_IDLE

[!(~ pi_host_reset)]

7

default

`REGS_IDLE

[!(~ pi_host_reset)]

Instances