Module ip_mac_tx_bkoff_g

ip_mac_tx_bkoff_g u_ip_mac_tx_bkoff_g ( .pi_reset(pi_reset), .pi_g_clock(pi_g_clock), .pi_f_clock(pi_f_clock), .po_en_clock(po_en_clock), .pi_bk_reset(pi_bk_reset), .pi_bk_start(pi_bk_start), .pi_half_duplex(pi_half_duplex), .pi_hd_fc_enable(pi_hd_fc_enable), .po_bk_done(po_bk_done) );

Block Diagram of ip_mac_tx_bkoff_g

When a transmission attempt has terminated due to a collision, it is retried by the transmitting CSMA/CD sublayer until either it is successful or a maximum number of attempts have been made and all have terminated due to collisions. Note that all attempts to transmit a given frame are completed before any subsequent outgoing frames are transmitted. The scheduling of the retransmissions is determined by a controlled randomization process called truncated binary exponential backoff.

At the end of enforcing

a collision (jamming), the CSMA/CD sublayer delays before attempting to retransmit the frame. The delay is an integer multiple of 512 bit time slot. The number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range:

-1 < r < 2 power k, where k = min (n, 10)

If all n attempts limit fails, this event is reported as an error. Algorithms used to generate the integer r should be designed to minimize the correlation between the numbers generated by any two stations at any given time.

Note: The values given above define the most aggressive behavior that a station may exhibit in attempting to retransmit after a collision. In the course of implementing the retransmission scheduling procedure, a station may introduce extra delays that will degrade its own throughput, but in no case may a station retransmission scheduling result in a lower average delay between retransmission attempts than the procedure defined above.

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Hardware/Software reset (active low)
pi_g_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, gated clock)
pi_f_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, free clock)
po_en_clock	reg	output	Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable
pi_bk_reset	wire logic	input	Backoff interface Backoff counter reset command
pi_bk_start	wire logic	input	Backoff algorithm start command
pi_half_duplex	wire logic	input	Operating Half Duplex mode
pi_hd_fc_enable	wire logic	input	Half-Duplex Flow Control enable
po_bk_done	reg	output	Backoff done indication

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

Generate Backoff Done

always @ ( posedge pi_f_clock or negedge pi_reset )

Clock Gating Module

FSM Transitions for bk_state

#	Current State	Next State	Condition	Comment
1	`BK_IDLE	`BK_DONE	[(!(~ pi_reset) && (pi_bk_start == 1'b1))]
2	`BK_DONE	`BK_IDLE	[(!(~ pi_reset) && (bk_ended == slot_cnt && pi_hd_fc_enable == 1'b0)), (!(~ pi_reset) && !(bk_ended == slot_cnt && pi_hd_fc_enable == 1'b0) && (pi_hd_fc_enable == 1'b1))]

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_tx_top : ip_mac_tx_top_g

      • tx_bkoff : ip_mac_tx_bkoff_g

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