Module ip_mac_fc_dec_g

ip_mac_fc_dec_g u_ip_mac_fc_dec_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_g_clock(pi_g_clock), .po_en_clock(po_en_clock), .pi_gigabit(pi_gigabit), .pi_xmit_nfc(pi_xmit_nfc), .pi_fc_enable(pi_fc_enable), .pi_fc_toggle(pi_fc_toggle), .pi_fc_value(pi_fc_value), .po_fc_tx_off(po_fc_tx_off) );

Block Diagram of ip_mac_fc_dec_g

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Software/Hardware Reset (receive clock domain)
pi_f_clock	wire logic	input	Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_g_clock	wire logic	input	Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_en_clock	reg	output	Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_xmit_nfc	wire logic	input	Transmit FSM data frame transmit enable (when full duplex)
pi_fc_enable	wire logic	input	NOTE: This signal is not asserted during flow control frame transmission Receive flow control enable (flow control decoding enable)
pi_fc_toggle	wire logic	input	New pause frame received (pi_fc_value valid)
pi_fc_value	wire logic [15 : 0]	input	Pause time (from RX EMAC, FC frame decoding)
po_fc_tx_off	reg	output	Received FC packet (Transmit stop command)

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

FC Transmit OFF Process

always @ ( posedge pi_f_clock or negedge pi_reset )

Clock Gating Module

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • fc_dec : ip_mac_fc_dec_g

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