Module ip_mac_hostif_arb

ip_mac_hostif_arb u_ip_mac_hostif_arb ( .pi_reset(pi_reset), .pi_clock(pi_clock), .pi_tx_frame_transmit(pi_tx_frame_transmit), .pi_regs_csr0_bar(pi_regs_csr0_bar), .pi_rx_req(pi_rx_req), .pi_tx_req(pi_tx_req), .pi_rx_ds_req(pi_rx_ds_req), .pi_tx_ds_req(pi_tx_ds_req), .pi_tx_upd_req(pi_tx_upd_req), .pi_rx_mcmd(pi_rx_mcmd), .pi_rx_maddr(pi_rx_maddr), .pi_rx_mdata(pi_rx_mdata), .pi_rx_mlast(pi_rx_mlast), .pi_tx_mcmd(pi_tx_mcmd), .pi_tx_maddr(pi_tx_maddr), .pi_tx_mlast(pi_tx_mlast), .pi_rx_ds_mcmd(pi_rx_ds_mcmd), .pi_rx_ds_maddr(pi_rx_ds_maddr), .pi_rx_ds_mlast(pi_rx_ds_mlast), .pi_tx_ds_mcmd(pi_tx_ds_mcmd), .pi_tx_ds_maddr(pi_tx_ds_maddr), .pi_tx_ds_mlast(pi_tx_ds_mlast), .pi_tx_upd_mcmd(pi_tx_upd_mcmd), .pi_tx_upd_maddr(pi_tx_upd_maddr), .pi_tx_upd_mdata(pi_tx_upd_mdata), .pi_tx_upd_mlast(pi_tx_upd_mlast), .po_host_mcmd(po_host_mcmd), .po_host_maddr(po_host_maddr), .po_host_mdata(po_host_mdata), .po_host_mlast(po_host_mlast), .po_rx_allowed(po_rx_allowed), .po_rx_ds_allowed(po_rx_ds_allowed), .po_tx_allowed(po_tx_allowed), .po_tx_ds_allowed(po_tx_ds_allowed), .po_tx_upd_allowed(po_tx_upd_allowed) );

Block Diagram of ip_mac_hostif_arb

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous pi_reset
pi_clock	wire logic	input	host pi_clock
pi_tx_frame_transmit	wire logic	input	from pi_mac_hostif_tx
pi_regs_csr0_bar	wire logic	input	from banks regs
pi_rx_req	wire logic	input
pi_tx_req	wire logic	input
pi_rx_ds_req	wire logic	input
pi_tx_ds_req	wire logic	input
pi_tx_upd_req	wire logic	input
pi_rx_mcmd	wire logic [1 : 0]	input
pi_rx_maddr	wire logic [31 : 0]	input
pi_rx_mdata	wire logic [31 : 0]	input
pi_rx_mlast	wire logic	input
pi_tx_mcmd	wire logic [1 : 0]	input
pi_tx_maddr	wire logic [31 : 0]	input
pi_tx_mlast	wire logic	input	pi_tx_mdata,
pi_rx_ds_mcmd	wire logic [1 : 0]	input
pi_rx_ds_maddr	wire logic [31 : 0]	input
pi_rx_ds_mlast	wire logic	input
pi_tx_ds_mcmd	wire logic [1 : 0]	input
pi_tx_ds_maddr	wire logic [31 : 0]	input
pi_tx_ds_mlast	wire logic	input
pi_tx_upd_mcmd	wire logic [1 : 0]	input
pi_tx_upd_maddr	wire logic [31 : 0]	input
pi_tx_upd_mdata	wire logic [31 : 0]	input
pi_tx_upd_mlast	wire logic	input
po_host_mcmd	reg [1 : 0]	output
po_host_maddr	reg [31 : 0]	output
po_host_mdata	reg [31 : 0]	output
po_host_mlast	reg	output
po_rx_allowed	reg	output
po_rx_ds_allowed	reg	output
po_tx_allowed	reg	output
po_tx_ds_allowed	reg	output
po_tx_upd_allowed	reg	output

Always Blocks

always @ ( posedge pi_clock or negedge pi_reset )

---

process for arbiter *

---

always @ ( arb_state or pi_rx_req or pi_tx_req or pi_rx_ds_req or pi_tx_ds_req or pi_tx_upd_req )

arbiter allowed calculation pi_tx_frame_transmit

always @ ( arb_state or po_rx_allowed or po_tx_allowed or po_rx_ds_allowed or po_tx_ds_allowed or po_tx_upd_allowed )

arbiter next state calculation

FSM Transitions for arb_state

#	Current State	Next State	Condition	Comment
1	`ARB_IDLE	`ARB_S0	[!(~ pi_reset)]

always @ ( po_rx_allowed or po_tx_allowed or po_rx_ds_allowed or po_tx_ds_allowed or po_tx_upd_allowed or pi_rx_mcmd or pi_rx_maddr or pi_rx_mdata or pi_rx_mlast or pi_tx_mcmd or pi_tx_maddr or pi_tx_mlast or pi_rx_ds_mcmd or pi_rx_ds_maddr or pi_rx_ds_mlast or pi_tx_ds_mcmd or pi_tx_ds_maddr or pi_tx_ds_mlast or pi_tx_upd_mcmd or pi_tx_upd_maddr or pi_tx_upd_mdata or pi_tx_upd_mlast )

arbiter multiplexor

Instances

• ip_emac_top : ip_emac_top

  • host_if : ip_mac_hostif_top

    • hostif_arb : ip_mac_hostif_arb

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