Module ip_mac_hostif_txds

Block Diagram of ip_mac_hostif_txds

Ports
Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous pi_reset
pi_g_clock	wire logic	input	host pi_g_clock
pi_f_clock	wire logic	input	host pi_g_clock
po_en_clock	reg	output	enable clock condition
po_tx_ds_req	reg	output	output
po_tx_ds_addr	reg [31 : 0]	output	output , mapped to old tx_ds_next_addr
po_tx_ds_addr_valid	reg	output	output
po_tx_ds_mlast	reg	output	output
po_tx_ds_mcmd	reg [1 : 0]	output	output
po_tx_ds_maddr	wire logic [31 : 0]	output	output
pi_tx_valid_ds_read	wire logic	input	from pi_mac_hostif_tx (signals that new ds polling is enabled)
pi_host_sdva	wire logic	input
pi_host_sdata	wire logic [31 : 0]	input
pi_tx_ds_allowed	wire logic	input	pi_host_serr, //from host interface
po_tx_ds0_poll	reg [31 : 0]	output
pi_tx_ds1	wire logic [1 : 0]	input	mapped to tx pi_tx_ds1[25:24]
pi_tx_ds3	wire logic [31 : 0]	input
pi_regs_csr0_tap	wire logic [15 : 0]	input	Registers bank interface tx automatic polling period CSR0[31:16]
pi_regs_csr0_ape	wire logic	input	tx auto polling enable CSR[15]
pi_regs_csr1_tpd	wire logic	input	transmit poll demand
pi_regs_csr3_stl	wire logic [29 : 0]	input	transmit descriptor base address
po_regs_csr5_tu	reg	output	transmit buffer unavailable
pi_regs_csr14_st	wire logic	input	start/stop transmit
pi_config_ds_offset	wire logic [4 : 0]	input	offset to increment the address if a descriptor

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset ) : manages the next descriptor aquire

FSM Transitions for tx_ds_state
#	Current State	Next State	Condition
1	`TX_DS_IDLE	`TX_DS_MAIN	[(!(~ pi_reset) && !(! pi_regs_csr14_st))]
2	`TX_DS_MAIN	`TX_DS_READ	[(!(~ pi_reset) && (pi_tx_ds_allowed))]
3	`TX_DS_READ	`TX_DS_WAIT	[(!(~ pi_reset) && (pi_host_sdva) && (pi_host_sdata[31]))]
4	`TX_DS_READ	`TX_DS_SUSPEND	[(!(~ pi_reset) && (pi_host_sdva) && !(pi_host_sdata[31]))]
5	`TX_DS_WAIT	`TX_DS_MAIN	[(!(~ pi_reset) && (pi_tx_valid_ds_read))]
6	`TX_DS_SUSPEND	`TX_DS_MAIN	[(!(~ pi_reset) && (pi_regs_csr0_ape && tx_ds_poll_cnt == pi_regs_csr0_tap \|\| pi_regs_csr1_tpd))]