Module ip_mac_top_g

TX_MEM_ADDRRX_MEM_ADDRpi_emac_resetlogicpi_emac_sw_resetlogicpi_emac_ref_clocklogicpi_emac_gate_enlogicpi_emac_power_offlogicpi_emac_tx_clocklogicpi_emac_tx_collogicpi_emac_tx_crslogicpi_emac_rx_clocklogicpi_emac_rx_dvlogicpi_emac_rx_errlogicpi_emac_rx_data[7:0]logicpi_host_clocklogicpi_host_stat_readlogicpi_host_enable_wrlogicpi_host_data_wr[31:0]logicpi_host_byte_wr[1:0]logicpi_host_start_wrlogicpi_host_end_wrlogicpi_host_error_wrlogicpi_host_pad_wrlogicpi_host_crc_wrlogicpi_host_wakeuplogicpi_host_wr_data[31:0]logicpi_host_wr_setuplogicpi_host_enable_rdlogicpi_host_stop_xmitlogicpi_host_stop_rcvlogicpi_emac_gigabitlogicpi_emac_half_dplxlogicpi_emac_xoff_value[15:0]logicpi_emac_xon_value[15:0]logicpi_emac_col_limit[4:0]logicpi_emac_tx_fc_enlogicpi_emac_burst_lim[15:0]logicpi_emac_burst_enlogicpi_emac_ifg_cfg_1[7:0]logicpi_emac_ifg_cfg_2[7:0]logicpi_emac_store_fwdlogicpi_emac_threshold[TX_MEM_ADDR-1:0]logicpi_emac_rx_fc_enlogicpi_emac_hash_nfixlogicpi_emac_inverselogicpi_emac_multicastlogicpi_emac_pass_multilogicpi_emac_promisclogicpi_emac_pass_alllogicpi_emac_high_thrs[RX_MEM_ADDR:0]logicpi_emac_low_thrs[RX_MEM_ADDR:0]logicpi_emac_loopbacklogicpi_emac_littlelogicpi_mdio_clocklogicpi_master_mdiologicpi_emac_mdc_wdata[15:0]logicpi_host_mdc_startlogicpi_emac_mdc_rnwlogicpi_emac_mdc_daddr[4:0]logicpi_emac_mdc_raddr[4:0]logicpi_test_enlogicpi_bistmode_enlogicpo_host_tx_idonelogicpo_host_rx_idonelogicpo_emac_gtx_clocklogicpo_emac_tx_enlogicpo_emac_tx_errlogicpo_emac_tx_datalogic[7:0]po_host_stat_emptylogicpo_host_stat_lastlogicpo_host_stat_datalogic[9:0]po_host_full_wrlogicpo_host_last_wrlogicpo_host_empty_rdlogicpo_host_last_rdlogicpo_host_data_rdlogic[31:0]po_host_byte_rdlogic[1:0]po_host_start_rdlogicpo_host_end_rdlogicpo_host_error_rdlogicpo_host_stop_xmitlogicpo_host_stop_rcvlogicpo_master_mdclogicpo_master_mdiologicpo_master_onilogicpo_emac_mdc_errlogicpo_emac_mdc_rdatalogic[15:0]po_emac_mdc_donelogic

Block Diagram of ip_mac_top_g

Parameters

Name

Default

Description
TX_MEM_ADDR

9

Transmit memory address width (9 -> 512 locations, 10->1024)
RX_MEM_ADDR

6

Receive memory address width (9 -> 512 locations, 10->1024)
Ports

Name

Type

Direction

Description
pi_emac_reset

wire logic

input

Global Hardware reset (active low)
pi_emac_sw_reset

wire logic

input

Global Software reset (active high) (should be applied whenever

pi_emac_ref_clock

wire logic

input

GMII 125 MHz reference clock
pi_emac_gate_en

wire logic

input

Auto Gating Clock Enable (power saving)

pi_emac_power_off

wire logic

input

Power off (all internal clocks are disabled, except for the HOST clock)
po_host_tx_idone

wire logic

output

Transmit/Receive reset (initialization) done Transmit initialization done (host clock domain)
po_host_rx_idone

wire logic

output

Receive initialization done (host clock domain)
pi_emac_tx_clock

wire logic

input

Transmit GMII/MII interface Transmit MII 25/2.5 MHz clock (from PHY)
po_emac_gtx_clock

wire logic

output

Transmit GMII 125 MHz clock (to PHY)
po_emac_tx_en

wire logic

output

Transmit MII/GMII enable indication (to PHY)
po_emac_tx_err

wire logic

output

Transmit MII/GMII error indication (to PHY)
po_emac_tx_data

wire logic [7 : 0]

output

Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY)
pi_emac_tx_col

wire logic

input

Collision indication (from PHY)
pi_emac_tx_crs

wire logic

input

Carrier Sense indication (from PHY)
pi_emac_rx_clock

wire logic

input

Receive GMII/MII interface Receive GMII/MII 125/25/2.5 MHz clock (from PHY)
pi_emac_rx_dv

wire logic

input

Receive MII/GMII data valid indication (from PHY)
pi_emac_rx_err

wire logic

input

Receive MII/GMII error indication (from PHY)
pi_emac_rx_data

wire logic [7 : 0]

input

Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY)
pi_host_clock

wire logic

input

HOST interface (common) HOST interface clock signal
pi_host_stat_read

wire logic

input

Transmit statistic HOST interface Statistic TDES0 word
[8] = jabber,[7] = late collision, [6] = excess collision,[5:2] = collision counter [1] = underrun,[0] = deferred Read statistic word command
po_host_stat_empty

wire logic

output

Statistic FIFO not empty
po_host_stat_last

wire logic

output

Last statistic word indication

po_host_stat_data

wire logic [9 : 0]

output

Statistic TDES0 word data
pi_host_enable_wr

wire logic

input

Tramsmit data path HOST interface Transmit MAC data path, HOST enable command
po_host_full_wr

wire logic

output

Transmit MAC data path, HOST FIFO full indication
po_host_last_wr

wire logic

output

Transmit MAC data path, HOST FIFO last location indication
pi_host_data_wr

wire logic [31 : 0]

input

Transmit MAC data path, HOST data (transmit data)
pi_host_byte_wr

wire logic [1 : 0]

input

Transmit MAC data path, HOST byte enable (transmit data byte enable)
pi_host_start_wr

wire logic

input

Transmit MAC data path, HOST start of frame indication
pi_host_end_wr

wire logic

input

Transmit MAC data path, HOST start of frame indication
pi_host_error_wr

wire logic

input

Unused please check if useful (if not remove)
pi_host_pad_wr

wire logic

input

Transmit MAC data path, HOST padding enable (valid only when pi_host_end_wr)
pi_host_crc_wr

wire logic

input

Transmit MAC data path, HOST crc enable (valid only when pi_host_end_wr)
pi_host_wakeup

wire logic

input

Receive setup frame interface (not affected by software reset, setup frame is written during software reset) Wake-up internal clock used by the Setup Frame FSM,

pi_host_wr_data

wire logic [31 : 0]

input

should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be deasserted 2 clock cycles after Setup Frame completition Setup Frame data (HOST clock synchronous)
pi_host_wr_setup

wire logic

input

Setup Frame write enable (HOST clock synchronous)
pi_host_enable_rd

wire logic

input

Receive data path HOST interface Receive MAC data path, HOST enable command
po_host_empty_rd

wire logic

output

Receive MAC data path, HOST FIFO empty indication
po_host_last_rd

wire logic

output

Receive MAC data path, HOST FIFO last location indication
po_host_data_rd

wire logic [31 : 0]

output

Receive MAC data path, HOST data (transmit data)
po_host_byte_rd

wire logic [1 : 0]

output

Receive MAC data path, HOST byte enable (transmit data byte enable)
po_host_start_rd

wire logic

output

Receive MAC data path, HOST start of frame indication
po_host_end_rd

wire logic

output

Receive MAC data path, HOST start of frame indication
po_host_error_rd

wire logic

output

Receive MAC data path, HOST frame error indication (asserted when
po_host_stop_xmit

wire logic

output

frame is bigger than 64 bytes and receive MAC cannot drop the frame or pass bad frames mode is selected by asserting pi_emac_pass_all) Start/Stop transmit and receive process Transmit MAC, transmit stopped indication (HOST clock synchronous)
pi_host_stop_xmit

wire logic

input

Transmit MAC, transmit stop command (HOST clock synchronous)
po_host_stop_rcv

wire logic

output

Receive MAC, receive stopped indication (HOST clock synchronous)
pi_host_stop_rcv

wire logic

input

Receive MAC, receive stop command (HOST clock synchronous)
pi_emac_gigabit

wire logic

input

Operating 1000 Mbps (Gigabit) mode
pi_emac_half_dplx

wire logic

input

Operating Half Duplex mode
pi_emac_xoff_value

wire logic [15 : 0]

input

Transmit configuration inputs (require software reset to be active during change)
XOFF flow control pause value
pi_emac_xon_value

wire logic [15 : 0]

input

XON flow control pause value
pi_emac_col_limit

wire logic [4 : 0]

input

Half Duplex back pressure collision limit

pi_emac_tx_fc_en

wire logic

input

(maximum collision number during back pressure algorithm) Transmit flow control enable
pi_emac_burst_lim

wire logic [15 : 0]

input

Burst limit (valid only when operating mode is 1000 Mbps)
pi_emac_burst_en

wire logic

input

Burst enable (valid only when operating mode is 1000 Mbps)
pi_emac_ifg_cfg_1

wire logic [7 : 0]

input

Interframe gap part 1 (usually 2/3 from IFG)
pi_emac_ifg_cfg_2

wire logic [7 : 0]

input

Interframe gap part 2 (usually 1/3 from IFG)
pi_emac_store_fwd

wire logic

input

Store and Forward transmit FIFO operating mode
pi_emac_threshold

wire logic [TX_MEM_ADDR - 1 : 0]

input

Cut Trough (pi_emac_store_fwd not asserted) FIFO threshold

pi_emac_rx_fc_en

wire logic

input

Receive configuration inputs (require software reset to be active during change)
Receive flow control enable (flow control decoding enable)
pi_emac_hash_nfix

wire logic

input

Hash filtering + 1 Address match / 16 Address match
pi_emac_inverse

wire logic

input

Inverse match filtering mode
pi_emac_multicast

wire logic

input

When asserted the imperfect filtering refers only for multicast addressees
pi_emac_pass_multi

wire logic

input

Pass all multicast addresses
pi_emac_promisc

wire logic

input

Promiscuous Mode (no DA filter)
pi_emac_pass_all

wire logic

input

pass all bad frames (including FC frames)
pi_emac_high_thrs

wire logic [RX_MEM_ADDR : 0]

input

from configuration FC high threshold
pi_emac_low_thrs

wire logic [RX_MEM_ADDR : 0]

input

from configuration FC low threshold
pi_emac_loopback

wire logic

input

Miscelanous configuration inputs (require software reset to be active during change)
Loopback mode select
pi_emac_little

wire logic

input

Little endian (data path organization)
pi_mdio_clock

wire logic

input

Management Data Input/Output interface (MDIO) Master MDIO reference clock

po_master_mdc

wire logic

output

Master MDIO output 2.5 MHz clock

pi_master_mdio

wire logic

input

Master MDIO data input line (tri-state buffer outside of the module)
po_master_mdio

wire logic

output

Master MDIO data output line (tri-state buffer outside of the module)
po_master_oni

wire logic

output

Master MDIO direction tri-state buffer control (1 - Output, 0 - Input)
po_emac_mdc_err

wire logic

output

Indicates that a read from MDIO interface is invalid and the

pi_emac_mdc_wdata

wire logic [15 : 0]

input

operation should be retried. This is indicated during a read turn-around cycle when the MDIO slave does not drive the MDIO signal to the low state. MDIO transaction complete. (MDIO clock domain, remain asserted till pi_host_mdc_start is deasserted) MDIO write data (not synchronized, false path, needs to be stable durring pi_host_mdc_start)
po_emac_mdc_rdata

wire logic [15 : 0]

output

MDIO read data (not synchronized, false path, needs to be stable durring pi_host_mdc_start)
pi_host_mdc_start

wire logic

input

(MDIO clock domain, remain stable till pi_host_mdc_start is deasserted) Setting this bit initiates an MDIO read/write operation (asynchronous,

po_emac_mdc_done

wire logic

output

internally synchronized to MDC clock). Remain asserted till the transaction complete. MDIO transaction complete.
pi_emac_mdc_rnw

wire logic

input

(MDIO clock domain, remain asserted till pi_host_mdc_start is deasserted) This bit indicates the direction of the MDIO operation type:
pi_emac_mdc_daddr

wire logic [4 : 0]

input

0 - MDIO Write operation, 1 - MDIO read operation (not synchronized, false path, needs to be stable during pi_host_mdc_start) This field is used to specify the device address to be accessed.
pi_emac_mdc_raddr

wire logic [4 : 0]

input

(not synchronized, false path, needs to be stable during pi_host_mdc_start) This field is used to specify the register address to be accessed.
pi_test_en

wire logic

input

(not synchronized, false path, needs to be stable during pi_host_mdc_start) Test and Scan interface signals
Test mode enable
pi_bistmode_en

wire logic

input

Instances

Submodules

mac_clk_mng (ip_mac_clk_mng_g) pi_reset pi_sw_reset pi_gate_en po_host_reset po_host_hw_rst po_mdio_hw_rst po_tx_reset po_rx_reset pi_power_off pi_mdio_clock pi_host_clock pi_host_clock_en pi_ref_clock po_gtx_clock pi_tx_clock pi_tx_clock_en pi_rx_clock pi_rx_clock_en pi_loopback pi_gigabit po_mdio_clock_f po_host_clock_f po_host_clock_g po_tx_clock_f po_tx_clock_g po_rx_clock_f po_rx_clock_g pi_test_en pi_bistmode_en mac_mdio (ip_mac_mdio_g) pi_reset pi_clock pi_master_mdio po_master_mdio po_master_oni po_mdio_err pi_mdio_wdata po_mdio_rdata pi_mdio_start po_mdio_done pi_mdio_rnw pi_mdio_daddr pi_mdio_raddr mac_rx_top (ip_mac_rx_top_g) pi_rx_reset pi_host_reset pi_host_hw_rst pi_rx_f_clock pi_rx_g_clock po_rx_en_clock po_host_init_done pi_tx_gmii_val pi_tx_gmii_err pi_tx_gmii_data pi_tx_xmit_nfc pi_rx_gmii_sel pi_gmii_val pi_gmii_data pi_gmii_err pi_rx_gigabit pi_rx_half_duplex pi_rx_loopback pi_rx_fc_enable po_rx_fc_tx_off po_rx_fc_xoff_tgl po_rx_fc_xon_tgl pi_host_hash_nfix pi_host_little pi_rx_hash_nfix pi_rx_inverse pi_rx_multicast pi_rx_pass_multi pi_rx_promisc pi_rx_pass_all pi_rx_high_thrs pi_rx_low_thrs pi_host_wakeup pi_host_wr_data pi_host_wr_setup pi_host_f_clock pi_host_g_clock po_host_en_clock pi_host_enable_rd po_host_empty_rd po_host_last_rd po_host_data_rd po_host_byte_rd po_host_start_rd po_host_end_rd po_host_error_rd pi_host_stop_rcv po_host_stop_rcv mac_tx_top (ip_mac_tx_top_g) pi_tx_reset pi_host_reset pi_tx_f_clock pi_tx_g_clock po_tx_en_clock po_host_init_done pi_host_stop_xmit po_host_stop_xmit pi_rx_fc_xoff_tgl pi_rx_fc_xon_tgl pi_tx_xoff_value pi_tx_xon_value pi_tx_col_limit pi_tx_fc_enable pi_rx_fc_tx_off pi_tx_gigabit pi_tx_burst_lim pi_tx_burst_en pi_tx_half_duplex pi_tx_ifg_cfg_1 pi_tx_ifg_cfg_2 pi_tx_store_fwd pi_tx_threshold po_tx_xmit_nfc po_gmii_en po_gmii_err po_gmii_data pi_gmii_col pi_gmii_crs pi_host_stat_read po_host_stat_empty po_host_stat_last po_host_stat_data pi_host_clock pi_host_little pi_host_enable_wr po_host_full_wr po_host_last_wr pi_host_data_wr pi_host_byte_wr pi_host_start_wr pi_host_end_wr pi_host_error_wr pi_host_pad_wr pi_host_crc_wr mac_top (ip_mac_top_g) pi_emac_reset pi_emac_sw_reset pi_emac_ref_clock pi_emac_gate_en pi_emac_power_off po_host_tx_idone po_host_rx_idone pi_emac_tx_clock po_emac_gtx_clock po_emac_tx_en po_emac_tx_err po_emac_tx_data pi_emac_tx_col pi_emac_tx_crs pi_emac_rx_clock pi_emac_rx_dv pi_emac_rx_err pi_emac_rx_data pi_host_clock pi_host_stat_read po_host_stat_empty po_host_stat_last po_host_stat_data pi_host_enable_wr po_host_full_wr po_host_last_wr pi_host_data_wr pi_host_byte_wr pi_host_start_wr pi_host_end_wr pi_host_error_wr pi_host_pad_wr pi_host_crc_wr pi_host_wakeup pi_host_wr_data pi_host_wr_setup pi_host_enable_rd po_host_empty_rd po_host_last_rd po_host_data_rd po_host_byte_rd po_host_start_rd po_host_end_rd po_host_error_rd po_host_stop_xmit pi_host_stop_xmit po_host_stop_rcv pi_host_stop_rcv pi_emac_gigabit pi_emac_half_dplx pi_emac_xoff_value pi_emac_xon_value pi_emac_col_limit pi_emac_tx_fc_en pi_emac_burst_lim pi_emac_burst_en pi_emac_ifg_cfg_1 pi_emac_ifg_cfg_2 pi_emac_store_fwd pi_emac_threshold pi_emac_rx_fc_en pi_emac_hash_nfix pi_emac_inverse pi_emac_multicast pi_emac_pass_multi pi_emac_promisc pi_emac_pass_all pi_emac_high_thrs pi_emac_low_thrs pi_emac_loopback pi_emac_little pi_mdio_clock po_master_mdc pi_master_mdio po_master_mdio po_master_oni po_emac_mdc_err pi_emac_mdc_wdata po_emac_mdc_rdata pi_host_mdc_start po_emac_mdc_done pi_emac_mdc_rnw pi_emac_mdc_daddr pi_emac_mdc_raddr pi_test_en pi_bistmode_en

Schematic Diagram of ip_mac_top_g