Module ip_mac_tx_gmii_g

ip_mac_tx_gmii_g u_ip_mac_tx_gmii_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_gigabit(pi_gigabit), .pi_half_duplex(pi_half_duplex), .pi_burst_en(pi_burst_en), .pi_ifg_cfg_1(pi_ifg_cfg_1), .pi_ifg_cfg_2(pi_ifg_cfg_2), .po_deferring(po_deferring), .po_deferred(po_deferred), .pi_gmii_busy(pi_gmii_busy), .pi_gmii_en(pi_gmii_en), .pi_gmii_err(pi_gmii_err), .po_gmii_crs(po_gmii_crs), .pi_gmii_crs(pi_gmii_crs), .pi_gmii_col(pi_gmii_col) );

Block Diagram of ip_mac_tx_gmii_g

Frames are transmitted over the EMAC MII/GMII interface with an interframe gap which is specified by the IEEE 802.3-2002 standard to be 96 bit times (9.6 us for 10 Mbps, 0.96 us for 100 Mbps, 0.096 us for 1000 Mbps). This is a minimum value and may be increased with a resulting decrease in throughput (results in a less aggressive approach to gain access to a shared Ethernet bus). The process for deferring the transmission is different for half-duplex and full-duplex systems and is as follows:

Half-Duplex Even when it has nothing to transmit, the EMAC monitors the bus for traffic by watching the carrier sense signal from the external PHY. Whenever the bus is busy, the EMAC defers to the passing frame by delaying any pending transmission of its own. After the last bit of the passing frame (when carrier sense signal changes from true to false), the EMAC starts the timing of the interframe gap. The EMAC will reset the interframe gap timer if carrier sense becomes true during the first period defined by the IFG1. The IEEE 802.3-2002 standard states that this should be the first 2/3 of the interframe gap interval (64 bit times) but may be shorter and as small as zero. The EMAC will not reset the interframe gap timer if carrier sense becomes true during the period defined by the second IFG2 field to ensure fair access to the bus. The IEEE 802.3-2002 standard states that this should be the last 1/3 of the interframe gap timing interval (32 bit times) but may be longer and as large as the whole interframe gap time.

Full-Duplex The EMAC does not use the carrier sense signal from the external PHY when in full duplex mode since the bus is not shared and only needs to monitor its own transmissions. After the last bit of an EMAC transmission, the EMAC starts the interframe gap timer and defers transmissions until it has reached the value represented by the combination of the IFG1 and IFG2.

The EMAC Transmit MII/GMII module is responsible also to demultilex the GMII interface signals coming from EMAC Transmit State Machine into MII format (nibble oriented) when 10/100 Mbps operating mode is selected or to pass the GMII signal to the output when 1000 Mbps operating mode.
The GMII/MII block is responsible to register the input signals comming from the physical layer, and synchronize the carrier sense indication (two DFF's are required since the carrier sense is an asynchronous input)

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Hardware/Software reset (active low)
pi_f_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_half_duplex	wire logic	input	Defer interface Operating Half Duplex mode
pi_burst_en	wire logic	input	Burst enable (valid only when operating mode is 1000 Mbps)
pi_ifg_cfg_1	wire logic [7 : 0]	input	Interframe gap part 1 (usualy 2/3 from IFG)
pi_ifg_cfg_2	wire logic [7 : 0]	input	Interframe gap part 2 (usualy 1/3 from IFG)
po_deferring	wire logic	output	Defer current transmition (when asserted high)
po_deferred	reg	output	Statistic information (frame was deferred)
pi_gmii_busy	wire logic	input	Tx MAC state interface
pi_gmii_en	wire logic	input	Transmit GMII enable indication
pi_gmii_err	wire logic	input	Transmit GMII error indication
po_gmii_crs	reg	output	Carrier Sense indication
pi_gmii_crs	wire logic	input	MII Transmit Enable and Data Output Signals, Carrier Sense and Colision Indicators Carrier Sense indication Asynchronous input (2 DFF required for synchronization) (from PHY)
pi_gmii_col	wire logic	input	Collision indication (from PHY)

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset )

Input MII/GMII Signals Synchronization

always @ ( negedge pi_f_clock or negedge pi_reset )

Falling edge (inverted clock used for first synchronization DFF) always @(posedge pi_i_clock or negedge pi_reset)

always @ ( defer_state or pi_gmii_en or gmii_col or pi_half_duplex or gmii_crs or pi_gmii_err or pi_gmii_busy or counter or pi_burst_en or gmii_busy_del )

Defer MII/GMII FSM

always @ ( posedge pi_f_clock or negedge pi_reset )

Defer Counter

FSM Transitions for defer_state

#	Current State	Next State	Condition	Comment
1	`TX_BEGIN	`TX_CARRIER	[EMPTY]
2	`TX_CARRIER	`TX_JAM	[(pi_gmii_en == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1)]
3	`TX_CARRIER	`TX_ERROR	[(!(pi_gmii_en == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1) && (pi_gmii_err == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1))]
4	`TX_CARRIER	`TX_IDLE	[(!(pi_gmii_en == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1) && (pi_gmii_busy == 1'b1))]
5	`TX_CARRIER	`TX_IFG2	[(!(pi_gmii_en == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && pi_gmii_busy == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_busy == 1'b1) && !(gmii_crs == 1'b1) && (counter == 9'd0))]
6	`TX_JAM	`TX_CARRIER	[(counter == 9'd1)]
7	`TX_ERROR	`TX_CARRIER	[(counter == 9'd1)]
8	`TX_IDLE	`TX_JAM	[(pi_gmii_en == 1'b1 && gmii_col == 1'b1)]
9	`TX_IDLE	`TX_ERROR	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && (pi_gmii_err == 1'b1 && gmii_col == 1'b1))]
10	`TX_IDLE	`TX_IFG1	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_busy == 1'b1) && (pi_gmii_busy == 1'b0 && gmii_busy_del == 1'b1 && gmii_crs == 1'b0 || pi_burst_en == 1'b1))]
11	`TX_IDLE	`TX_WAIT	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_busy == 1'b1) && !(pi_gmii_busy == 1'b0 && gmii_busy_del == 1'b1 && gmii_crs == 1'b0 || pi_burst_en == 1'b1) && (pi_gmii_busy == 1'b0 && gmii_busy_del == 1'b1))]
12	`TX_IDLE	`TX_CARRIER	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_busy == 1'b1) && !(pi_gmii_busy == 1'b0 && gmii_busy_del == 1'b1 && gmii_crs == 1'b0 || pi_burst_en == 1'b1) && !(pi_gmii_busy == 1'b0 && gmii_busy_del == 1'b1) && (gmii_crs == 1'b1 && pi_gmii_en == 1'b0 && pi_gmii_err == 1'b0))]
13	`TX_IFG2	`TX_ERROR	[(pi_gmii_err == 1'b1 && gmii_col == 1'b1)]
14	`TX_IFG2	`TX_LATENCY	[(!(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && (counter == 9'd0))]
15	`TX_IFG1	`TX_ERROR	[(pi_gmii_err == 1'b1 && gmii_col == 1'b1)]
16	`TX_IFG1	`TX_IFG2	[(!(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && (counter == 9'd0))]
17	`TX_WAIT	`TX_JAM	[(pi_gmii_en == 1'b1 && gmii_col == 1'b1)]
18	`TX_WAIT	`TX_ERROR	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && (pi_gmii_err == 1'b1 && gmii_col == 1'b1))]
19	`TX_WAIT	`TX_IFG1	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && (gmii_crs == 1'b0))]
20	`TX_LATENCY	`TX_JAM	[(pi_gmii_en == 1'b1 && gmii_col == 1'b1)]
21	`TX_LATENCY	`TX_ERROR	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && (pi_gmii_err == 1'b1 && gmii_col == 1'b1))]
22	`TX_LATENCY	`TX_IDLE	[(!(pi_gmii_en == 1'b1 && gmii_col == 1'b1) && !(pi_gmii_err == 1'b1 && gmii_col == 1'b1) && (counter == 9'd0))]
23	default	`TX_BEGIN	[EMPTY]

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_tx_top : ip_mac_tx_top_g

      • tx_gmii : ip_mac_tx_gmii_g

×