Module ip_sync_cell

pi_reset_wrlogicpi_reset_rdlogicpi_clock_wrlogicpi_clock_rdlogicpi_ready_wrlogicpi_ready_rdlogicpo_enable_wrlogicpo_enable_rdlogic

Block Diagram of ip_sync_cell

The synchronization cell is responsible for the write/read enable signals synchronization. The write enable signal indicates that a new write clock domain data can be synchronized to the read clock domain. The read enable signal indicates that the external data can be safely read on the read clock domain.

Ports

Name

Type

Direction

Description
pi_reset_wr

wire logic

input

reset write clock domain (synchronous)
pi_reset_rd

wire logic

input

reset read clock domain (synchronous)
pi_clock_wr

wire logic

input

write clock
pi_clock_rd

wire logic

input

read clock

po_enable_wr

wire logic

output

write enable (combinatorial output)

po_enable_rd

wire logic

output

read enable (combinatorial output)

pi_ready_wr

wire logic

input

write ready (data available for write)
pi_ready_rd

wire logic

input

read ready (data available for read)

Always Blocks

always @ ( posedge pi_clock_rd or negedge pi_reset_rd )

syncronized toggle write (synchronization second DFF)

always @ ( posedge pi_clock_wr or negedge pi_reset_wr )

syncronized toggle read (synchronization second DFF)

Instances

Submodules

metastable_toggle_rd (dff_metastable) reset d clock q metastable_toggle_wr (dff_metastable) reset d clock q po_enable_rd toggle_wr_sync_rd toggle_rd po_enable_wr toggle_wr toggle_rd_sync_wr toggle_rd pi_reset_rd pi_clock_rd toggle_rd po_enable_rd pi_ready_rd toggle_wr_sync_rd pi_reset_rd pi_clock_rd toggle_wr_metast toggle_wr pi_reset_wr pi_clock_wr toggle_wr po_enable_wr pi_ready_wr toggle_rd_sync_wr pi_reset_wr pi_clock_wr toggle_rd_metast cell_0 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd

Schematic Diagram of ip_sync_cell