Module ip_mac_clk_mng_g

pi_resetlogicpi_sw_resetlogicpi_gate_enlogicpi_power_offlogicpi_mdio_clocklogicpi_host_clocklogicpi_host_clock_enlogicpi_ref_clocklogicpi_tx_clocklogicpi_tx_clock_en[3:0]logicpi_rx_clocklogicpi_rx_clock_en[2:0]logicpi_loopbacklogicpi_gigabitlogicpi_test_enlogicpi_bistmode_enlogicpo_host_resetlogicpo_host_hw_rstlogicpo_mdio_hw_rstlogicpo_tx_resetlogicpo_rx_resetlogicpo_gtx_clocklogicpo_mdio_clock_flogicpo_host_clock_flogicpo_host_clock_glogicpo_tx_clock_flogicpo_tx_clock_glogic[3:0]po_rx_clock_flogicpo_rx_clock_glogic[2:0]

Block Diagram of ip_mac_clk_mng_g

Ports

Name

Type

Direction

Description

pi_reset

wire logic

input

Resets Hardware reset (active low)

pi_sw_reset

wire logic

input

Software reset (active high)

pi_gate_en

wire logic

input

Auto Gating Clock Enable (power saving)

po_host_reset

wire logic

output

Hardware/Software Global output reset (HOST clock domain)

po_host_hw_rst

wire logic

output

Hardware Global output reset (HOST clock domain)

po_mdio_hw_rst

wire logic

output

Hardware MDIO output reset (MDIO clock domain)

po_tx_reset

wire logic

output

Hardware/Software Global output reset (transmit clock domain)

po_rx_reset

wire logic

output

Hardware/Software Global output reset (receive clock domain)

pi_power_off

wire logic

input

Power OFF Power off (all internal clocks are disabled)

pi_mdio_clock

wire logic

input

Clocks MDIO clock used by the MDIO module

pi_host_clock

wire logic

input

HOST clock used by the reset synchronization block

pi_host_clock_en

wire logic

input

HOST clock enable

pi_ref_clock

wire logic

input

125 MHz Reference Clock

po_gtx_clock

wire logic

output

GMII Transmit clock (balanced with the EMAC internal clock)

pi_tx_clock

wire logic

input

Transmit 25/2.5 MHz Clock (from PHY)

pi_tx_clock_en

wire logic [3 : 0]

input

Enable Transmit 25/2.5 MHz Clock (from PHY)

pi_rx_clock

wire logic

input

Receive 125/25/2.5 MHz Clock (from PHY)

pi_rx_clock_en

wire logic [2 : 0]

input

Enable Receive 125/25/2.5 MHz Clock (from PHY)

pi_loopback

wire logic

input

Operating Mode Information MUX clock domain to TX Clock domain

pi_gigabit

wire logic

input

Clocks divider/MUX information

po_mdio_clock_f

wire logic

output

Output MDIO clock MDIO clock used by the MDIO module

po_host_clock_f

wire logic

output

Output Host Clock
Host Free Clock

po_host_clock_g

wire logic

output

Host Gated Clock

po_tx_clock_f

wire logic

output

Output Transmit Clocks
Transmit Free 125/25/12.5 MHz Clock for external interface

po_tx_clock_g

wire logic [3 : 0]

output

po_tx_clock_if , // Transmit Inverted Free 125/25/12.5 MHz Clock for external interface Transmit Gated 125/25/12.5 MHz Clock for external interface

po_rx_clock_f

wire logic

output

Output Receive Clocks
Receive Free 125/25/12.5 MHz clock for external interface

po_rx_clock_g

wire logic [2 : 0]

output

Receive Gated 125/25/12.5 MHz clock for external interface

pi_test_en

wire logic

input

Test and Scan interface signals
Test enable (test clock select)

pi_bistmode_en

wire logic

input

Instances

Submodules

gtx_clock_out (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock host_free_clock (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock host_gate_clock_1 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock host_sreset (ip_sync_reset_g) pi_reset pi_clock pi_test_en po_reset hw_host_sreset (ip_sync_reset_g) pi_reset pi_clock pi_test_en po_reset mdio_free_clock (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock mdio_sreset (ip_sync_reset_g) pi_reset pi_clock pi_test_en po_reset rx_free_clock (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock rx_gate_clock_1 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock rx_gate_clock_2 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock rx_gate_clock_3 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock rx_sreset (ip_sync_reset_g) pi_reset pi_clock pi_test_en po_reset tx_free_clock (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock tx_gate_clock_1 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock tx_gate_clock_2 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock tx_gate_clock_3 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock tx_gate_clock_4 (ip_gate_clock_g) pi_clock pi_enable pi_test_en pi_bistmode_en po_clock tx_sreset (ip_sync_reset_g) pi_reset pi_clock pi_test_en po_reset sw_hw_reset pi_reset pi_test_en pi_sw_reset rx_mux_clock pi_rx_clock pi_test_en pi_loopback tx_mux_clock tx_mux_clock pi_ref_clock pi_test_en pi_gigabit pi_tx_clock tx_en_clock sw_hw_reset pi_power_off pi_tx_clock_en pi_gate_en rx_en_clock sw_hw_reset pi_power_off pi_rx_clock_en pi_gate_en host_en_clock sw_hw_reset pi_power_off pi_host_clock_en pi_gate_en mac_clk_mng (ip_mac_clk_mng_g) pi_reset pi_sw_reset pi_gate_en po_host_reset po_host_hw_rst po_mdio_hw_rst po_tx_reset po_rx_reset pi_power_off pi_mdio_clock pi_host_clock pi_host_clock_en pi_ref_clock po_gtx_clock pi_tx_clock pi_tx_clock_en pi_rx_clock pi_rx_clock_en pi_loopback pi_gigabit po_mdio_clock_f po_host_clock_f po_host_clock_g po_tx_clock_f po_tx_clock_g po_rx_clock_f po_rx_clock_g pi_test_en pi_bistmode_en

Schematic Diagram of ip_mac_clk_mng_g