Module ip_mac_clk_mng_g

ip_mac_clk_mng_g u_ip_mac_clk_mng_g ( .pi_reset(pi_reset), .pi_sw_reset(pi_sw_reset), .pi_gate_en(pi_gate_en), .po_host_reset(po_host_reset), .po_host_hw_rst(po_host_hw_rst), .po_mdio_hw_rst(po_mdio_hw_rst), .po_tx_reset(po_tx_reset), .po_rx_reset(po_rx_reset), .pi_power_off(pi_power_off), .pi_mdio_clock(pi_mdio_clock), .pi_host_clock(pi_host_clock), .pi_host_clock_en(pi_host_clock_en), .pi_ref_clock(pi_ref_clock), .po_gtx_clock(po_gtx_clock), .pi_tx_clock(pi_tx_clock), .pi_tx_clock_en(pi_tx_clock_en), .pi_rx_clock(pi_rx_clock), .pi_rx_clock_en(pi_rx_clock_en), .pi_loopback(pi_loopback), .pi_gigabit(pi_gigabit), .po_mdio_clock_f(po_mdio_clock_f), .po_host_clock_f(po_host_clock_f), .po_host_clock_g(po_host_clock_g), .po_tx_clock_f(po_tx_clock_f), .po_tx_clock_g(po_tx_clock_g), .po_rx_clock_f(po_rx_clock_f), .po_rx_clock_g(po_rx_clock_g), .pi_test_en(pi_test_en), .pi_bistmode_en(pi_bistmode_en) );

Block Diagram of ip_mac_clk_mng_g

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Resets Hardware reset (active low)
pi_sw_reset	wire logic	input	Software reset (active high)
pi_gate_en	wire logic	input	Auto Gating Clock Enable (power saving)
po_host_reset	wire logic	output	Hardware/Software Global output reset (HOST clock domain)
po_host_hw_rst	wire logic	output	Hardware Global output reset (HOST clock domain)
po_mdio_hw_rst	wire logic	output	Hardware MDIO output reset (MDIO clock domain)
po_tx_reset	wire logic	output	Hardware/Software Global output reset (transmit clock domain)
po_rx_reset	wire logic	output	Hardware/Software Global output reset (receive clock domain)
pi_power_off	wire logic	input	Power OFF Power off (all internal clocks are disabled)
pi_mdio_clock	wire logic	input	Clocks MDIO clock used by the MDIO module
pi_host_clock	wire logic	input	HOST clock used by the reset synchronization block
pi_host_clock_en	wire logic	input	HOST clock enable
pi_ref_clock	wire logic	input	125 MHz Reference Clock
po_gtx_clock	wire logic	output	GMII Transmit clock (balanced with the EMAC internal clock)
pi_tx_clock	wire logic	input	Transmit 25/2.5 MHz Clock (from PHY)
pi_tx_clock_en	wire logic [3 : 0]	input	Enable Transmit 25/2.5 MHz Clock (from PHY)
pi_rx_clock	wire logic	input	Receive 125/25/2.5 MHz Clock (from PHY)
pi_rx_clock_en	wire logic [2 : 0]	input	Enable Receive 125/25/2.5 MHz Clock (from PHY)
pi_loopback	wire logic	input	Operating Mode Information MUX clock domain to TX Clock domain
pi_gigabit	wire logic	input	Clocks divider/MUX information
po_mdio_clock_f	wire logic	output	Output MDIO clock MDIO clock used by the MDIO module
po_host_clock_f	wire logic	output	Output Host Clock Host Free Clock
po_host_clock_g	wire logic	output	Host Gated Clock
po_tx_clock_f	wire logic	output	Output Transmit Clocks Transmit Free 125/25/12.5 MHz Clock for external interface
po_tx_clock_g	wire logic [3 : 0]	output	po_tx_clock_if , // Transmit Inverted Free 125/25/12.5 MHz Clock for external interface Transmit Gated 125/25/12.5 MHz Clock for external interface
po_rx_clock_f	wire logic	output	Output Receive Clocks Receive Free 125/25/12.5 MHz clock for external interface
po_rx_clock_g	wire logic [2 : 0]	output	Receive Gated 125/25/12.5 MHz clock for external interface
pi_test_en	wire logic	input	Test and Scan interface signals Test enable (test clock select)
pi_bistmode_en	wire logic	input

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_clk_mng : ip_mac_clk_mng_g

Submodules

• ip_mac_clk_mng_g

  • gtx_clock_out : ip_gate_clock_g

  • host_free_clock : ip_gate_clock_g

  • host_gate_clock_1 : ip_gate_clock_g

  • host_sreset : ip_sync_reset_g

  • hw_host_sreset : ip_sync_reset_g

  • mdio_free_clock : ip_gate_clock_g

  • mdio_sreset : ip_sync_reset_g

  • rx_free_clock : ip_gate_clock_g

  • rx_gate_clock_1 : ip_gate_clock_g

  • rx_gate_clock_2 : ip_gate_clock_g

  • rx_gate_clock_3 : ip_gate_clock_g

  • rx_sreset : ip_sync_reset_g

  • tx_free_clock : ip_gate_clock_g

  • tx_gate_clock_1 : ip_gate_clock_g

  • tx_gate_clock_2 : ip_gate_clock_g

  • tx_gate_clock_3 : ip_gate_clock_g

  • tx_gate_clock_4 : ip_gate_clock_g

  • tx_sreset : ip_sync_reset_g

Schematic Diagram of ip_mac_clk_mng_g

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