Module ip_mac_hostif_rxds

ip_mac_hostif_rxds u_ip_mac_hostif_rxds ( .pi_reset(pi_reset), .pi_g_clock(pi_g_clock), .pi_f_clock(pi_f_clock), .po_en_clock(po_en_clock), .pi_host_sdva(pi_host_sdva), .pi_host_sdata(pi_host_sdata), .pi_rx_ds_allowed(pi_rx_ds_allowed), .pi_rx_empty(pi_rx_empty), .pi_rx_last_rd(pi_rx_last_rd), .po_rx_ds_next_addr(po_rx_ds_next_addr), .po_rx_ds_addr_valid(po_rx_ds_addr_valid), .po_rx_ds_mlast(po_rx_ds_mlast), .po_rx_ds_mcmd(po_rx_ds_mcmd), .po_rx_ds_req(po_rx_ds_req), .po_rx_ds_maddr(po_rx_ds_maddr), .pi_rx_valid_ds_read(pi_rx_valid_ds_read), .pi_rx_ds1(pi_rx_ds1), .pi_rx_ds3(pi_rx_ds3), .pi_regs_csr2_rpd(pi_regs_csr2_rpd), .pi_regs_csr4_srl(pi_regs_csr4_srl), .po_regs_csr5_ru(po_regs_csr5_ru), .pi_regs_csr14_sr(pi_regs_csr14_sr), .pi_config_ds_offset(pi_config_ds_offset) );

Block Diagram of ip_mac_hostif_rxds

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global interface global asynchronous pi_reset
pi_g_clock	wire logic	input	host gated clock
pi_f_clock	wire logic	input	host free clock
po_en_clock	reg	output	enable clock condition
pi_host_sdva	wire logic	input
pi_host_sdata	wire logic [31 : 0]	input	mapped to pi_host_sdata[31]
pi_rx_ds_allowed	wire logic	input
pi_rx_empty	wire logic	input
pi_rx_last_rd	wire logic	input
po_rx_ds_next_addr	reg [31 : 0]	output	output
po_rx_ds_addr_valid	reg	output	output
po_rx_ds_mlast	reg	output	output
po_rx_ds_mcmd	reg [1 : 0]	output	output
po_rx_ds_req	reg	output	output
po_rx_ds_maddr	wire logic [31 : 0]	output	output
pi_rx_valid_ds_read	wire logic	input	input
pi_rx_ds1	wire logic [1 : 0]	input	holds current rx descriptor body mapped to rx, pi_rx_ds1[25:24]
pi_rx_ds3	wire logic [31 : 0]	input
pi_regs_csr2_rpd	wire logic	input	Registers bank interface receive poll demand
pi_regs_csr4_srl	wire logic [29 : 0]	input	receive descriptor base address
po_regs_csr5_ru	reg	output	receive buffer unavailable
pi_regs_csr14_sr	wire logic	input	start / stop receive
pi_config_ds_offset	wire logic [4 : 0]	input	offset to increment the address if a descriptor

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

manages the next descriptor aquire when rx_ds_needed is asserted, asserts po_rx_ds_req when pi_host_arb_ds_dv is asserted load pi_host_arb_ds_data into current_ds_addr and deasserts po_host_arb_ds_req the one that asserted ds_needed waits for pi_host_arb_ds_dv to pi_reset

always @ ( posedge pi_f_clock or negedge pi_reset )

Gated Clock Enable

FSM Transitions for rx_ds_state

#	Current State	Next State	Condition	Comment
1	`RX_DS_IDLE	`RX_DS_MAIN	[(!(~ pi_reset) && !(! pi_regs_csr14_sr))]
2	`RX_DS_MAIN	`RX_DS_READ	[(!(~ pi_reset) && (pi_rx_ds_allowed))]
3	`RX_DS_READ	`RX_DS_WAIT	[(!(~ pi_reset) && (pi_host_sdva) && (pi_host_sdata))]
4	`RX_DS_READ	`RX_DS_SUSPEND	[(!(~ pi_reset) && (pi_host_sdva) && !(pi_host_sdata))]
5	`RX_DS_WAIT	`RX_DS_MAIN	[(!(~ pi_reset) && (pi_rx_valid_ds_read))]
6	`RX_DS_SUSPEND	`RX_DS_MAIN	[(!(~ pi_reset) && (rx_mac_ds_poll || pi_regs_csr2_rpd))]

Instances

• ip_emac_top : ip_emac_top

  • host_if : ip_mac_hostif_top

    • hostif_rxds : ip_mac_hostif_rxds

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