Module ip_mac_hostif_top
Block Diagram of ip_mac_hostif_top
Name |
Type |
Direction |
Description |
|---|---|---|---|
pi_reset |
wire logic |
input |
|
pi_clock_f |
wire logic |
input |
host clock |
pi_rx_clock |
wire logic |
input |
|
pi_rxds_clock |
wire logic |
input |
|
pi_tx_clock |
wire logic |
input |
|
pi_txds_clock |
wire logic |
input |
|
pi_tx1_clock |
wire logic |
input |
|
po_rx_clock_en |
wire logic |
output |
clock enable for gated clocks |
po_rxds_clock_en |
wire logic |
output |
|
po_tx_clock_en |
wire logic |
output |
|
po_txds_clock_en |
wire logic |
output |
|
po_tx1_clock_en |
wire logic |
output |
|
po_host_mcmd |
wire logic [1 : 0] |
output |
command |
po_host_maddr |
wire logic [31 : 0] |
output |
address |
po_host_mdata |
wire logic [31 : 0] |
output |
data to write |
po_host_mlast |
wire logic |
output |
last word |
pi_host_sdata |
wire logic [31 : 0] |
input |
data to read |
pi_host_sdva |
wire logic |
input |
data valid |
po_rx_enable_rd |
wire logic |
output |
rx fifo read command |
pi_rx_empty |
wire logic |
input |
rx fifo full |
pi_rx_last_rd |
wire logic |
input |
rx fifo almost full |
pi_rx_data |
wire logic [31 : 0] |
input |
rx fifo data |
pi_rx_sof |
wire logic |
input |
rx fifo eof |
pi_rx_eof |
wire logic |
input |
rx fifo eof |
po_tx_enable_wr |
wire logic |
output |
rx fifo read command |
pi_tx_full |
wire logic |
input |
rx fifo full |
pi_tx_last_wr |
wire logic |
input |
rx fifo almost full |
po_tx_data |
wire logic [31 : 0] |
output |
rx fifo data |
po_tx_be |
wire logic [1 : 0] |
output |
tx fifo data byte enable |
po_tx_sof |
wire logic |
output |
tx fifo start of frame |
po_tx_eof |
wire logic |
output |
tx fifo end of frame |
po_tx_err |
wire logic |
output |
tx fifo error |
po_tx_put_crc |
wire logic |
output |
put crc indication (valid only when sof=1) |
po_tx_put_padding |
wire logic |
output |
put padding indication (valid only when sof=1) |
po_tx_upd_read |
wire logic |
output |
|
pi_tx_upd_empty |
wire logic |
input |
|
pi_tx_upd_last |
wire logic |
input |
|
pi_tx_upd_data |
wire logic [9 : 0] |
input |
|
pi_regs_csr0_tap |
wire logic [15 : 0] |
input |
tx automatic polling period CSR0[31:16] |
pi_regs_csr0_ape |
wire logic |
input |
tx auto polling enable CSR[15] |
pi_regs_csr0_bar |
wire logic |
input |
bus arbitration |
pi_regs_csr14_swr |
wire logic |
input |
software reset |
pi_regs_csr1_tpd |
wire logic |
input |
transmit poll demand |
pi_regs_csr2_rpd |
wire logic |
input |
receive poll demand |
pi_regs_csr3_stl |
wire logic [29 : 0] |
input |
transmit descriptor base address |
pi_regs_csr4_srl |
wire logic [29 : 0] |
input |
receive descriptor base address |
po_regs_csr5_rwt |
wire logic |
output |
receive watchdog timeout |
po_regs_csr5_unf |
wire logic |
output |
transmit underflow |
po_regs_csr5_ovf |
wire logic |
output |
receive overflow |
po_regs_csr5_ru |
wire logic |
output |
receive buffer unavailable |
po_regs_csr5_tu |
wire logic |
output |
transmit buffer unavailable |
po_regs_csr5_ri |
wire logic |
output |
receive interupt |
po_regs_csr5_ti |
wire logic |
output |
transmit interupt |
po_regs_csr5_tjt |
wire logic |
output |
signals Transmit jabber timeout error to the CSR5 register; this will signal to the HOST to perform a software reset to the EMAC |
pi_regs_csr14_st |
wire logic |
input |
start/stop transmit |
pi_regs_csr14_sr |
wire logic |
input |
start / stop receive |
pi_global_cfda_slm |
wire logic |
input |
sleep mode enable |
pi_global_cfda_szm |
wire logic |
input |
snooze mode enable |
pi_config_burst_size |
wire logic [5 : 0] |
input |
limit for the rx,tx burst transfers |
pi_config_ds_offset |
wire logic [4 : 0] |
input |
offset to increment the address if a descriptor |
Instances
- ip_emac_top : ip_emac_top
host_if : ip_mac_hostif_top
Submodules
- ip_mac_hostif_top
hostif_arb : ip_mac_hostif_arb
hostif_rx : ip_mac_hostif_rx
hostif_rxds : ip_mac_hostif_rxds
hostif_tx : ip_mac_hostif_tx
hostif_txds : ip_mac_hostif_txds
Schematic Diagram of ip_mac_hostif_top
global asynchronous reset