Module ip_mac_tx_fsm_g

ip_mac_tx_fsm_g u_ip_mac_tx_fsm_g ( .pi_reset(pi_reset), .pi_g_clock(pi_g_clock), .pi_f_clock(pi_f_clock), .po_en_clock(po_en_clock), .pi_sop(pi_sop), .pi_eop(pi_eop), .pi_pad(pi_pad), .pi_crc(pi_crc), .pi_valid(pi_valid), .pi_fc_req(pi_fc_req), .pi_data_req(pi_data_req), .po_fc_ack(po_fc_ack), .po_data_ack(po_data_ack), .po_read(po_read), .po_remove(po_remove), .po_reload(po_reload), .po_mac_state(po_mac_state), .po_update(po_update), .po_en_high(po_en_high), .pi_half_duplex(pi_half_duplex), .pi_hd_fc_en(pi_hd_fc_en), .pi_stop_xmit(pi_stop_xmit), .po_stop_xmit(po_stop_xmit), .po_bk_reset(po_bk_reset), .po_bk_start(po_bk_start), .pi_bk_done(pi_bk_done), .pi_deferring(pi_deferring), .pi_deferred(pi_deferred), .pi_gigabit(pi_gigabit), .pi_burst_lim(pi_burst_lim), .pi_burst_en(pi_burst_en), .po_burst_en(po_burst_en), .pi_gmii_en(pi_gmii_en), .pi_gmii_col(pi_gmii_col), .pi_gmii_crs(pi_gmii_crs), .po_xmit_nfc(po_xmit_nfc), .pi_stat_full(pi_stat_full), .po_stat_data(po_stat_data), .po_stat_load(po_stat_load) );

Block Diagram of ip_mac_tx_fsm_g

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Software/Hardware Reset (transmit clock domain)
pi_g_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, gated clock)
pi_f_clock	wire logic	input	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, free clock)
po_en_clock	reg	output	Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable
pi_sop	wire logic	input	Signals comming in from the data FIFO related to data transfer Start of data frame indication
pi_eop	wire logic	input	End of data frame indication
pi_pad	wire logic	input	Pad append command, valid only when end of frame (When padding enable
pi_crc	wire logic	input	and frame has less than 64 bytes the CRC is appended regardless of the CRC append setting CRC append command, valid only when end of frame
pi_valid	wire logic	input	Valid data
pi_fc_req	wire logic	input	Request & Acknowledge Flow control frame transmit request
pi_data_req	wire logic	input	Data frame transmit request
po_fc_ack	reg	output	Flow control frame transmit acknowledge
po_data_ack	reg	output	Data frame transmit acknowledge
po_read	reg	output	Read & Retransmit & Drop current frame Read next data
po_remove	reg	output	Remove current frame (drop frame)
po_reload	reg	output	Reload current frame (retransmit)
po_mac_state	reg [3 : 0]	output	Transmit FSM state Transmit FSM state current
po_update	reg	output	Collision window Collision window (update read pointer)
po_en_high	reg	output	Enable increment counter
pi_half_duplex	wire logic	input	Half duplex flow control enable Half duplex operating mode
pi_hd_fc_en	wire logic	input	Half-Duplex Flow Control enable
pi_stop_xmit	wire logic	input	Transmit start/stop Transmit EMAC stop command
po_stop_xmit	reg	output	Transmit EMAC stopped
po_bk_reset	reg	output	Control Signals Related to the Backoff Block Backoff counter reset command
po_bk_start	reg	output	Backoff algorithm start command
pi_bk_done	wire logic	input	Backoff done indication
pi_deferring	wire logic	input	Control Signal from the deferral counter Defer current transmition (when asserted high)
pi_deferred	wire logic	input	Deferred frame statistic information (asserted for one cycle)
pi_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_burst_lim	wire logic [15 : 0]	input	Burst limit (valid only when operating mode is 1000 Mbps)
pi_burst_en	wire logic	input	Burst enable (valid only when operating mode is 1000 Mbps)
po_burst_en	reg	output	Burst enable (valid only when operating mode is 1000 Mbps)
pi_gmii_en	wire logic	input	GMII Interface Transmit MII/GMII enable indication (to PHY)
pi_gmii_col	wire logic	input	Collision indication (from PHY)
pi_gmii_crs	wire logic	input	Carrier Sense indication (from PHY)
po_xmit_nfc	wire logic	output	(compensate the tx_gmii latency, connected to po_gmii_en on MII/GMII module) Transmit full duplex data frame transmit enable pending (non flow control frame is transmitted) Transmit FSM data frame transmit enable
pi_stat_full	wire logic	input	NOTE: This signal is not asserted during flow control frame transmission Statistic related signals Statistic FIFO full
po_stat_data	wire logic [9 : 0]	output	Statistic FIFO data
po_stat_load	reg	output	Statistic FIFO write enable signal

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

Carrier Sense Delay Process

always @ ( posedge pi_g_clock or negedge pi_reset )

General Counter 64 bytes and 512 bytes Detect

always @ ( posedge pi_g_clock or negedge pi_reset )

FIFO pointers Management

always @ ( posedge pi_g_clock or negedge pi_reset )

Backoff And Statistic Signals Generation

always @ ( posedge pi_g_clock or negedge pi_reset )

Backoff And Statistic Signals Generation

always @ ( posedge pi_g_clock or negedge pi_reset )

MAC State Decoder

FSM Transitions for force_col

#	Current State	Next State	Condition	Comment
1	1'b1	1'b0	[(!(~ pi_reset) && (po_mac_state == 4'h1)), (!(~ pi_reset) && (po_mac_state == 4'h1))]

always @ ( posedge pi_f_clock or negedge pi_reset )

FSM Transitions for po_mac_state

#	Current State	Next State	Condition	Comment
1	`TX_IDLE	`TX_ERROR	[(!(~ pi_reset) && (gmii_col == 1'b1 && po_burst_en == 1'b1))]
2	`TX_IDLE	`TX_STOP	[(!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && (stop_xmit == 1'b1))]
3	`TX_IDLE	`TX_DEFER	[(!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && !(stop_xmit == 1'b1) && (pi_fc_req == 1'b1)), (!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && !(stop_xmit == 1'b1) && !(pi_fc_req == 1'b1) && (pi_data_req == 1'b1))]
4	`TX_IDLE	`TX_PREAMBLE	[(!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && !(stop_xmit == 1'b1) && !(pi_fc_req == 1'b1) && !(pi_data_req == 1'b1) && (gmii_crs == 1'b1 && gmii_crs_del == 1'b0 && pi_hd_fc_en == 1'b1))]
5	`TX_ERROR	`TX_BACKOFF	[(!(~ pi_reset) && ({counter[1 : 0], po_en_high} == {1'b1, ~ pi_gigabit, pi_gigabit}))]
6	`TX_STOP	`TX_IDLE	[(!(~ pi_reset) && (stop_xmit == 1'b0))]
7	`TX_DEFER	`TX_ERROR	[(!(~ pi_reset) && (gmii_col == 1'b1 && po_burst_en == 1'b1))]
8	`TX_DEFER	`TX_PREAMBLE	[(!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && (pi_deferring == 1'b0 && pi_sop == 1'b1)), (!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && !(pi_deferring == 1'b0 && pi_sop == 1'b1) && !(pi_deferring == 1'b0 && force_col == 1'b1) && (pi_deferring == 1'b0))]
9	`TX_DEFER	`TX_IDLE	[(!(~ pi_reset) && !(gmii_col == 1'b1 && po_burst_en == 1'b1) && !(pi_deferring == 1'b0 && pi_sop == 1'b1) && (pi_deferring == 1'b0 && force_col == 1'b1))]
10	`TX_PREAMBLE	`TX_ERROR	[(!(~ pi_reset) && (gmii_col == 1'b1 && pi_gmii_en == 1'b0))]
11	`TX_PREAMBLE	`TX_JAM	[(!(~ pi_reset) && !(gmii_col == 1'b1 && pi_gmii_en == 1'b0) && (gmii_col == 1'b1))]
12	`TX_PREAMBLE	`TX_SFD	[(!(~ pi_reset) && !(gmii_col == 1'b1 && pi_gmii_en == 1'b0) && !(gmii_col == 1'b1) && ({counter[2 : 1], po_en_high} == {2'd3, 1'b1}))]
13	`TX_BACKOFF	`TX_IDLE	[(!(~ pi_reset) && (col_counter[4] == 1'b1 || window_out == 1'b1)), (!(~ pi_reset) && !(col_counter[4] == 1'b1 || window_out == 1'b1) && (pi_bk_done == 1'b1 && po_bk_start == 1'b0))]
14	`TX_JAM	`TX_BACKOFF	[(!(~ pi_reset) && ({counter[1 : 0], po_en_high} == {1'b1, ~ pi_gigabit | force_col, pi_gigabit | force_col}))]
15	`TX_SFD	`TX_JAM	[(!(~ pi_reset) && (po_en_high == 1'b1 && force_col == 1'b1 || gmii_col == 1'b1))]
16	`TX_SFD	`TX_DATA	[(!(~ pi_reset) && !(po_en_high == 1'b1 && force_col == 1'b1 || gmii_col == 1'b1) && (po_en_high == 1'b1))]
17	`TX_DATA	`TX_JAM	[(!(~ pi_reset) && (gmii_col == 1'b1))]
18	`TX_DATA	`TX_IDLE	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1)), (!(~ pi_reset) && !(gmii_col == 1'b1) && !(counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1) && (pi_valid == 1'b0 && po_en_high == 1'b1))]
19	`TX_DATA	`TX_PAD	[(!(~ pi_reset) && !(gmii_col == 1'b1) && !(counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1) && !(pi_valid == 1'b0 && po_en_high == 1'b1) && (int_eop == 1'b1 && count_60 == 1'b0 && pi_pad == 1'b1 && po_en_high == 1'b1))]
20	`TX_DATA	`TX_CRC	[(!(~ pi_reset) && !(gmii_col == 1'b1) && !(counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1) && !(pi_valid == 1'b0 && po_en_high == 1'b1) && !(int_eop == 1'b1 && count_60 == 1'b0 && pi_pad == 1'b1 && po_en_high == 1'b1) && (int_eop == 1'b1 && pi_crc == 1'b1 && po_en_high == 1'b1))]
21	`TX_DATA	`TX_EXTEND	[(!(~ pi_reset) && !(gmii_col == 1'b1) && !(counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1) && !(pi_valid == 1'b0 && po_en_high == 1'b1) && !(int_eop == 1'b1 && count_60 == 1'b0 && pi_pad == 1'b1 && po_en_high == 1'b1) && !(int_eop == 1'b1 && pi_crc == 1'b1 && po_en_high == 1'b1) && (int_eop == 1'b1 && count_512 == 1'b0 && burst_begin == 1'b1 && pi_half_duplex == 1'b1))]
22	`TX_DATA	`TX_CRS_JAM	[(!(~ pi_reset) && !(gmii_col == 1'b1) && !(counter[14] == 1'b1 && counter[0] == 1'b1 && po_en_high == 1'b1) && !(pi_valid == 1'b0 && po_en_high == 1'b1) && !(int_eop == 1'b1 && count_60 == 1'b0 && pi_pad == 1'b1 && po_en_high == 1'b1) && !(int_eop == 1'b1 && pi_crc == 1'b1 && po_en_high == 1'b1) && !(int_eop == 1'b1 && count_512 == 1'b0 && burst_begin == 1'b1 && pi_half_duplex == 1'b1) && (int_eop == 1'b1 && po_en_high == 1'b1))]
23	`TX_PAD	`TX_JAM	[(!(~ pi_reset) && (gmii_col == 1'b1))]
24	`TX_PAD	`TX_CRC	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (count_60 == 1'b1 && po_en_high == 1'b1))]
25	`TX_CRC	`TX_JAM	[(!(~ pi_reset) && (gmii_col == 1'b1))]
26	`TX_CRC	`TX_EXTEND	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (crc_counter == 2'd3 && count_512 == 1'b0 && burst_begin == 1'b1 && pi_half_duplex == 1'b1))]
27	`TX_CRC	`TX_CRS_JAM	[(!(~ pi_reset) && !(gmii_col == 1'b1) && !(crc_counter == 2'd3 && count_512 == 1'b0 && burst_begin == 1'b1 && pi_half_duplex == 1'b1) && ({crc_counter, po_en_high} == {2'd3, 1'b1}))]
28	`TX_EXTEND	`TX_ERROR	[(!(~ pi_reset) && (gmii_col == 1'b1))]
29	`TX_EXTEND	`TX_CRS_ERR	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (count_512 == 1'b1))]
30	`TX_CRS_JAM	`TX_JAM	[(!(~ pi_reset) && (gmii_col == 1'b1))]
31	`TX_CRS_JAM	`TX_IDLE	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (gmii_crs == 1'b0 || po_burst_en == 1'b1))]
32	`TX_CRS_ERR	`TX_ERROR	[(!(~ pi_reset) && (gmii_col == 1'b1))]
33	`TX_CRS_ERR	`TX_IDLE	[(!(~ pi_reset) && !(gmii_col == 1'b1) && (gmii_crs == 1'b0 || po_burst_en == 1'b1))]
34	default	`TX_IDLE	[!(~ pi_reset)]

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_tx_top : ip_mac_tx_top_g

      • tx_fsm : ip_mac_tx_fsm_g

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