Module ip_mac_rx_state_g

ip_mac_rx_state_g #( .MEM_ADDR(MEM_ADDR) ) u_ip_mac_rx_state_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_g_clock(pi_g_clock), .po_en_clock(po_en_clock), .pi_gmii_val(pi_gmii_val), .pi_gmii_data(pi_gmii_data), .pi_gmii_err(pi_gmii_err), .pi_gigabit(pi_gigabit), .pi_half_duplex(pi_half_duplex), .pi_loopback(pi_loopback), .pi_little(pi_little), .po_fc_toggle(po_fc_toggle), .po_fc_value(po_fc_value), .po_start(po_start), .po_end(po_end), .po_error(po_error), .po_byte(po_byte), .po_data(po_data), .pi_rd_addr(pi_rd_addr), .po_wr_addr(po_wr_addr), .po_wr_ptr(po_wr_ptr), .po_push(po_push), .pi_err_match(pi_err_match), .pi_match(pi_match), .pi_fc_match(pi_fc_match), .pi_pass_all(pi_pass_all), .po_hash_addr(po_hash_addr), .po_dest_addr(po_dest_addr), .po_new_match(po_new_match), .po_abort(po_abort), .pi_stop_rcv(pi_stop_rcv), .po_stop_rcv(po_stop_rcv) );

Block Diagram of ip_mac_rx_state_g

Parameters

Name	Default	Description
MEM_ADDR	6	Receive memory address width (9 -> 512 locations, 10->1024)

Ports

Name	Type	Direction	Description
pi_reset	wire logic	input	Global Hardware/Software reset (active low)
pi_f_clock	wire logic	input	Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_g_clock	wire logic	input	Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_en_clock	reg	output	Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_gmii_val	wire logic	input	gmii Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (from interface MII block)
pi_gmii_data	wire logic [7 : 0]	input	Receive MII/GMII error indication (from GMII block)
pi_gmii_err	wire logic	input	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from interface MII block)
pi_gigabit	wire logic	input	Operating 1000 Mbps (Gigabit) mode
pi_half_duplex	wire logic	input	Operating Half Duplex mode
pi_loopback	wire logic	input	Loopback information (frame received in loopback mode)
pi_little	wire logic	input	Little endian data format (used for statistic word translation)
po_fc_toggle	reg	output	Flow control Interface New pause frame received
po_fc_value	reg [15 : 0]	output	Pause time (from FC frame decoding FSM)
po_start	reg	output	Data Path Interface Start of data frame indication
po_end	reg	output	End of data frame indication
po_error	reg	output	Error indication (valid when end of frame or indicate statistic word)
po_byte	reg [1 : 0]	output	Byte enable command, valid only when end of frame
po_data	reg [31 : 0]	output	FIFO Data bus (frame data 32-bit word)
pi_rd_addr	wire logic [MEM_ADDR : 0]	input	FIFO Control Interface Used by EMAC Receive State to see the momory state (full/empty/ready)
po_wr_addr	reg [MEM_ADDR : 0]	output	Write address (memory write address)
po_wr_ptr	reg [MEM_ADDR : 0]	output	Used by RX FIFO to compute the memory state (full/empty/ready)
po_push	reg	output	Write enable command
pi_err_match	wire logic	input	Filterring Interface Address match error
pi_match	wire logic	input	Address match
pi_fc_match	wire logic	input	Address match (control frame address)
pi_pass_all	wire logic	input	Pass all frames (pass bad frames)
po_hash_addr	reg [8 : 0]	output	Hash table index (9-MSB of CRC calculation over 48-bit destination address)
po_dest_addr	reg [47 : 0]	output	Exact match (destination address of the frame)
po_new_match	reg	output	Start a new search (match address, or hash filtering, toggle signal when new match should be prformed)
po_abort	reg	output	Abort search (due to errors)
pi_stop_rcv	wire logic	input	Receive start/stop Receive MAC, receive stopped indication
po_stop_rcv	reg	output	Receive MAC, receive stop command

Always Blocks

always @ ( posedge pi_g_clock or negedge pi_reset )

External Data Memory Addresses

always @ ( posedge pi_g_clock or negedge pi_reset )

FIFO Write State

always @ ( posedge pi_g_clock or negedge pi_reset )

Statistic Word

always @ ( posedge pi_g_clock or negedge pi_reset )

General Counter

always @ ( posedge pi_g_clock or negedge pi_reset )

MAC State Decoder

always @ ( posedge pi_f_clock or negedge pi_reset )

FSM Transitions for wr_mac_state

#	Current State	Next State	Condition	Comment
1	`WR_IDLE	`WR_DATA	[(!(~ pi_reset) && (po_stop_rcv == 1'b0 && gmii_valid == 1'b1 && gmii_eop == 1'b0))]
2	`WR_DATA	`WR_EXTEND	[(!(~ pi_reset) && (gigabit_hd == 1'b1 && extend_ok == 1'b0 && gmii_eop == 1'b1))]
3	`WR_DATA	`WR_OVERRUN	[(!(~ pi_reset) && !(gigabit_hd == 1'b1 && extend_ok == 1'b0 && gmii_eop == 1'b1) && (gmii_eop == 1'b1) && (full == 1'b1)), (!(~ pi_reset) && !(gigabit_hd == 1'b1 && extend_ok == 1'b0 && gmii_eop == 1'b1) && !(gmii_eop == 1'b1) && (counter[1 : 0] == 2'b00 && full == 1'b1))]
4	`WR_DATA	`WR_STAT	[(!(~ pi_reset) && !(gigabit_hd == 1'b1 && extend_ok == 1'b0 && gmii_eop == 1'b1) && (gmii_eop == 1'b1) && !(full == 1'b1))]
5	`WR_EXTEND	`WR_OVERRUN	[(!(~ pi_reset) && (extend_ok == 1'b1) && (full == 1'b1)), (!(~ pi_reset) && !(extend_ok == 1'b1) && (gmii_ext == 1'b0) && (full == 1'b1))]
6	`WR_EXTEND	`WR_STAT	[(!(~ pi_reset) && (extend_ok == 1'b1) && !(full == 1'b1)), (!(~ pi_reset) && !(extend_ok == 1'b1) && (gmii_ext == 1'b0) && !(full == 1'b1))]
7	`WR_OVERRUN	`WR_STAT	[(!(~ pi_reset) && (full == 1'b0 && gmii_valid == 1'b0 && int_val == 1'b0))]
8	`WR_STAT	`WR_IDLE	[!(~ pi_reset)]

Functions

crc32_data8 ( logic[31:0] crc, logic[7:0] data )

CRC: 32 DATA: 8, POLY: 104C11DB7 next crc

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • rx_state : ip_mac_rx_state_g #(.MEM_ADDR(10))

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