Module ip_mac_rx_sync_g

ip_mac_rx_sync_g u_ip_mac_rx_sync_g ( .pi_rx_reset(pi_rx_reset), .pi_rx_f_clock(pi_rx_f_clock), .po_host_idone(po_host_idone), .pi_host_reset(pi_host_reset), .pi_host_f_clock(pi_host_f_clock), .pi_rx_stop(pi_rx_stop), .po_host_stop(po_host_stop), .pi_host_stop(pi_host_stop), .po_rx_stop(po_rx_stop), .pi_tx_xmit_nfc(pi_tx_xmit_nfc), .po_rx_xmit_nfc(po_rx_xmit_nfc) );

Block Diagram of ip_mac_rx_sync_g

Ports

Name	Type	Direction	Description
pi_rx_reset	wire logic	input	Receive clock and reset Global Hardware/Software reset (receive clock domain, active low)
pi_rx_f_clock	wire logic	input	Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
po_host_idone	reg	output	Reset done Receive initialisation done (host clock domain)
pi_host_reset	wire logic	input	Host clock and reset Global Hardware/Software reset (host clock domain, active low)
pi_host_f_clock	wire logic	input	Host clock (from Clock Manager)
pi_rx_stop	wire logic	input	Inputs -> Synchronized outputs Receive stop command acknowledge (receive clock domain)
po_host_stop	reg	output	Receive stop command acknowledge (synchronized to host clock domain)
pi_host_stop	wire logic	input	Receive stop command (host clock domain)
po_rx_stop	reg	output	Receive stop command (synchronized to receive clock domain)
pi_tx_xmit_nfc	wire logic	input	Transmit FSM data frame transmit enable (transmit clock domain)
po_rx_xmit_nfc	reg	output	NOTE: This signal is not asserted during flow control frame transmission Transmit FSM data frame transmit enable (synchronized to receive clock domain)

Always Blocks

always @ ( posedge pi_rx_f_clock or negedge pi_rx_reset )

Host to Receive clock domain synchronization

always @ ( posedge pi_host_f_clock or negedge pi_host_reset )

Receive to Host clock domain synchronization

Instances

• ip_emac_top : ip_emac_top

  • mac_top : ip_mac_top_g

    • mac_rx_top : ip_mac_rx_top_g

      • rx_sync : ip_mac_rx_sync_g

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