External Generated Diagrams

In order to generate diagrams using external scripts, the description needs to be enclosed between @DVT_DIAGRAM_START and @DVT_DIAGRAM_END pragmas:

//  @DVT_DIAGRAM_START
//      @program my_plant_uml_wrapper.sh
//      @output_file out/my_wave.svg
//      @input
//            @startuml
//            node foo
//            foo --> bar          : ∅
//            foo -[bold]-> bar1   : bold
//            foo -[dashed]-> bar2 : dashed
//            foo -[dotted]-> bar3 : dotted
//            foo -[hidden]-> bar4 : hidden
//            foo -[plain]-> bar5  : plain
//            @enduml
//  @DVT_DIAGRAM_END
//  The end
class spi_ctrl_reg_model;
// ...
endclass

Available options when writing custom diagram descriptions:

@program

MANDATORY Absolute path to the external diagram generator or the name of the diagram generator to be searched in $PATH (environment variables are supported)

@input_file

OPTIONAL The diagram description input, which will be passed to the program. Absolute path or relative to the current source file.

@input

OPTIONAL In the absence of an input file, you can write diagram description inline.

@output_file

OPTIONAL Path to the generated diagram. Absolute path or relative to the current source file. If not specified it will be generated under a temporary directory.

@args

OPTIONAL Additional arguments for the program.

@replace_params

OPTIONAL Replace module parameters and macros with their default value. Default value: false.

Important

DVT will invoke the generator as follows: @program @input_file @output_file @args

SystemVerilog module parameters and macros default values can also be passed to the input description using the following syntax:

  • #PARAMETER_NAME

  • `MACRO_NAME