Skip to content
DVT VHDL IDE User Guide
24.2.26 (14 November 2024)
Toggle navigation menu
⌘
K
DVT VHDL IDE User Guide
/
Refactoring
Refactoring
Rename Refactoring
Rename Port Across the Design Hierarchy
Extract to Variable
Add New Port to Entity
Add New Generic to Entity
Connect Instances Across the Design Hierarchy
Connect Instances Using New Ports
Structural Changes Preview Diagram
Refactoring Connect View
Code Factory
Rename Refactoring
Back to top