The PoC-Library Documentation

Note

This documentation is generated from the IP Core Library official repository, to illustrate Specador Documentation Generator functionalities:

• Good looking entity documentation: fifo_cc_got_tempgot

• Support for Wavedrom: ddrio_inout

• Support for finite state machines: arp_Wrapper

PoC - "Pile of Cores" provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy.

Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend.

Namespaces

• cache
• fifo
• io
• mem
• net
• xil