Entity gearbox_up_dc

Block Diagram of gearbox_up_dc

This module provides a upscaling gearbox with a dependent clock (dc) interface. It perfoems a 'byte' to 'word' collection. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain "Clock1"; output "Out_Data" is of clock domain "Clock2". The "In_Align" is required to mark the starting byte in the word. An optional input register can be added by enabling (ADD_INPUT_REGISTERS = TRUE).

Assertions:

• Clock periods of Clock1 and Clock2 MUST be multiples of each other.

• Clock1 and Clock2 MUST be phase aligned (related) to each other.

Generics

Name	Type	Default	Description
INPUT_BITS	positive	8	input bit width
INPUT_ORDER	T_BIT_ORDER	LSB_FIRST	LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1)
OUTPUT_BITS	positive	32	output bit width
ADD_INPUT_REGISTERS	boolean	FALSE	add input register @Clock1

Ports

Name	Type	Direction	Description
Clock1	std_logic	in	input clock domain
Clock2	std_logic	in	output clock domain
In_Align	std_logic	in	align word (one cycle high impulse)
In_Data	std_logic_vector	in	input word
Out_Data	std_logic_vector	out	output word
Out_Valid	std_logic	out	output is valid

• Architecture rtl of gearbox_up_dc
  • Functions

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