Entity stream_DeMux

Block Diagram of stream_DeMux

Generics

Name	Type	Default	Description
PORTS	positive	2
DATA_BITS	positive	8
META_BITS	natural	8
META_REV_BITS	natural	2

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
DeMuxControl	std_logic_vector	in	Control interface
In_Valid	std_logic	in	IN Port
In_Data	std_logic_vector	in
In_Meta	std_logic_vector	in
In_Meta_rev	std_logic_vector	out
In_SOF	std_logic	in
In_EOF	std_logic	in
In_Ack	std_logic	out
Out_Valid	std_logic_vector	out	OUT Ports
Out_Data	T_SLM	out
Out_Meta	T_SLM	out
Out_Meta_rev	T_SLM	in
Out_SOF	std_logic_vector	out
Out_EOF	std_logic_vector	out
Out_Ack	std_logic_vector	in

• Architecture rtl of stream_DeMux
  • Processes

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