Entity gearbox_down_dc

Block Diagram of gearbox_down_dc

This module provides a downscaling gearbox with a dependent clock (dc) interface. It perfoems a 'word' to 'byte' splitting. The default order is LITTLE_ENDIAN (starting at byte(0)). Input "In_Data" is of clock domain "Clock1"; output "Out_Data" is of clock domain "Clock2". Optional input and output registers can be added by enabling (ADD_***PUT_REGISTERS = TRUE).

Assertions:

• Clock periods of Clock1 and Clock2 MUST be multiples of each other.

• Clock1 and Clock2 MUST be phase aligned (related) to each other.

Generics

Name	Type	Default	Description
INPUT_BITS	positive	32	input bits ('words')
OUTPUT_BITS	positive	8	output bits ('byte')
OUTPUT_ORDER	T_BIT_ORDER	LSB_FIRST	LSB_FIRST: start at byte(0), MSB_FIRST: start at byte(n-1)
ADD_INPUT_REGISTERS	boolean	FALSE	add input register @Clock1
ADD_OUTPUT_REGISTERS	boolean	FALSE	add output register @Clock2

Ports

Name	Type	Direction	Description
Clock1	std_logic	in	input clock domain
Clock2	std_logic	in	output clock domain
In_Data	std_logic_vector	in	input word
Out_Data	std_logic_vector	out	output word

• Architecture rtl of gearbox_down_dc

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