[source]

Entity sort_lru_list

ELEMENTSKEY_BITSDATA_BITSINITIAL_ELEMENTSINITIAL_VALIDSClockstd_logicResetstd_logicInsertstd_logicRemovestd_logicDataIn[DATA_BITS - 1 downto 0]std_logic_vectorValidstd_logicDataOutstd_logic_vector[DATA_BITS - 1 downto 0]

Block Diagram of sort_lru_list

List storing (key, value) pairs. The least-recently inserted pair is outputed on DataOut if Valid = '1'. If Valid = '0', then the list empty.

The inputs Insert, Remove, DataIn, and Reset are synchronous to the rising-edge of the clock clock. All control signals are high-active.

Supported operations: Insert: Insert DataIn as recently used (key, value) pair. If

key is already within the list, then the corresponding value is updated and the pair is moved to the recently used position.

Remove: Remove (key, value) pair with the given key. The list is not

modified if key is not within the list.

Generics

Name

Type

Default

Description

ELEMENTS

positive

16

KEY_BITS

positive

4

DATA_BITS

positive

8

INITIAL_ELEMENTS

T_SLM

(0 to 15 => (0 to 7 => '0'))

INITIAL_VALIDS

std_logic_vector

(0 to 15 => '0')

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

Insert

std_logic

in

Remove

std_logic

in

DataIn

std_logic_vector

in

Valid

std_logic

out

DataOut

std_logic_vector

out