Architecture rtl of stream_Buffer
Name |
Description |
---|---|
T_WRITER_STATE |
|
T_READER_STATE |
Processes
- process @(DataFIFO_Full or In_EOF or In_SOF or In_Data or In_Valid or Writer_State)
# |
Current State |
Next State |
Condition |
Comment |
---|---|---|---|---|
1 |
ST_IDLE |
ST_FRAME |
[(In_Valid and In_SOF and not In_EOF = '1')] |
|
2 |
ST_FRAME |
ST_IDLE |
[(In_Valid and In_EOF and not DataFIFO_Full = '1')] |
- process @(DataFIFO_DataOut or DataFIFO_Valid or Out_Ack or Reader_State)
# |
Current State |
Next State |
Condition |
Comment |
---|---|---|---|---|
1 |
ST_IDLE |
ST_FRAME |
[(DataFIFO_Valid and not DataFIFO_DataOut(EOF_BIT) and Out_Ack = '1')] |
|
2 |
ST_FRAME |
ST_IDLE |
[(DataFIFO_Valid and DataFIFO_DataOut(EOF_BIT) and Out_Ack = '1')] |
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