[source]

Component comm_crc

GENBITSclkstd_logicsetstd_logicinit[GEN ' length - 2 downto 0]std_logic_vectorstepstd_logicdin[BITS - 1 downto 0]std_logic_vectorrmdstd_logic_vector[GEN ' length - 2 downto 0]zerostd_logic

Block Diagram of comm_crc

Calculates the Remainder of the Division by the Generator Polynomial GEN.

Generics

Name

Type

Initial Value

Description

GEN

bit_vector

Generator Polynom

BITS

positive

Number of Bits to be processed in parallel

Ports

Name

Direction

Type

Description

clk

in

std_logic

Clock

set

in

std_logic

Parallel Preload of Remainder

init

in

std_logic_vector

step

in

std_logic

Process Input Data (MSB first)

din

in

std_logic_vector

rmd

out

std_logic_vector

Remainder

zero

out

std_logic

Remainder is Zero