[source]

Entity stream_Mirror

PORTSDATA_BITSMETA_BITSMETA_LENGTHClockstd_logicResetstd_logicIn_Validstd_logicIn_Data[DATA_BITS - 1 downto 0]std_logic_vectorIn_SOFstd_logicIn_EOFstd_logicIn_Meta_Data[isum ( META_BITS ) - 1 downto 0]std_logic_vectorOut_Ack[PORTS - 1 downto 0]std_logic_vectorOut_Meta_rst[PORTS - 1 downto 0]std_logic_vectorOut_Meta_nxt[PORTS - 1 downto 0 , META_BITS ' length - 1 downto 0]T_SLMIn_Ackstd_logicIn_Meta_rststd_logicIn_Meta_nxtstd_logic_vector[META_BITS ' length - 1 downto 0]Out_Validstd_logic_vector[PORTS - 1 downto 0]Out_DataT_SLM[PORTS - 1 downto 0 , DATA_BITS - 1 downto 0]Out_SOFstd_logic_vector[PORTS - 1 downto 0]Out_EOFstd_logic_vector[PORTS - 1 downto 0]Out_Meta_DataT_SLM[PORTS - 1 downto 0 , isum ( META_BITS ) - 1 downto 0]

Block Diagram of stream_Mirror

Generics

Name

Type

Default

Description

PORTS

positive

2

DATA_BITS

positive

8

META_BITS

T_POSVEC

(0 => 8)

META_LENGTH

T_POSVEC

(0 => 16)

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

In_Valid

std_logic

in

IN Port

In_Data

std_logic_vector

in

In_SOF

std_logic

in

In_EOF

std_logic

in

In_Ack

std_logic

out

In_Meta_rst

std_logic

out

In_Meta_nxt

std_logic_vector

out

In_Meta_Data

std_logic_vector

in

Out_Valid

std_logic_vector

out

OUT Port

Out_Data

T_SLM

out

Out_SOF

std_logic_vector

out

Out_EOF

std_logic_vector

out

Out_Ack

std_logic_vector

in

Out_Meta_rst

std_logic_vector

in

Out_Meta_nxt

T_SLM

in

Out_Meta_Data

T_SLM

out