Entity arith_prng

Block Diagram of arith_prng

This module implementes a Pseudo-Random Number Generator (PRNG) with configurable bit count (BITS). This module uses an internal list of FPGA optimized polynomials from 3 to 168 bits. The polynomials have at most 5 tap positions, so that long shift registers can be inferred instead of single flip-flops.

The generated number sequence includes the value all-zeros, but not all-ones.

Generics

Name	Type	Default	Description
BITS	positive	32
SEED	std_logic_vector	"0"

Ports

Name	Type	Direction	Description
clk	std_logic	in
rst	std_logic	in	reset value to initial seed
got	std_logic	in	the current value has been got, and a new value should be calculated
val	std_logic_vector	out	the pseudo-random number

• Architecture rtl of arith_prng

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