Entity sortnet_OddEvenSort

Block Diagram of sortnet_OddEvenSort

Generics

Name	Type	Default	Description
INPUTS	positive	8	input count
KEY_BITS	positive	32	the first KEY_BITS of In_Data are used as a sorting critera (key)
DATA_BITS	positive	32	inclusive KEY_BITS
META_BITS	natural	2	additional bits, not sorted but delayed as long as In_Data
PIPELINE_STAGE_AFTER	natural	2	add a pipline stage after n sorting stages
ADD_INPUT_REGISTERS	boolean	FALSE
ADD_OUTPUT_REGISTERS	boolean	TRUE

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
Inverse	std_logic	in
In_Valid	std_logic	in
In_IsKey	std_logic	in
In_Data	T_SLM	in
In_Meta	std_logic_vector	in
Out_Valid	std_logic	out
Out_IsKey	std_logic	out
Out_Data	T_SLM	out
Out_Meta	std_logic_vector	out

• Architecture rtl of sortnet_OddEvenSort
  • Functions

×