Entity comm_crc

Block Diagram of comm_crc

Computes the Cyclic Redundancy Check (CRC) for a data packet as remainder of the polynomial division of the message by the given generator polynomial (GEN).

The computation is unrolled so as to process an arbitrary number of message bits per step. The generated CRC is independent from the chosen processing width.

Generics

Name	Type	Default	Description
GEN	bit_vector		Generator Polynomial
BITS	positive		Number of Bits to be processed in parallel
STARTUP_RMD	std_logic_vector	"0"
OUTPUT_REGS	boolean	true

Ports

Name	Type	Direction	Description
clk	std_logic	in	Clock
set	std_logic	in	Parallel Preload of Remainder
init	std_logic_vector	in
step	std_logic	in	Process Input Data (MSB first)
din	std_logic_vector	in
rmd	std_logic_vector	out	Remainder
zero	std_logic	out	Remainder is Zero

• Architecture rtl of comm_crc
  • Functions

×