Entity sync_Reset

Block Diagram of sync_Reset

This module synchronizes an asynchronous reset signal to the clock Clock. The Input can be asserted and de-asserted at any time. The Output is asserted asynchronously and de-asserted synchronously to the clock.

Attention

Use this synchronizer only to asynchronously reset your design. The 'Output' should be feed by global buffer to the destination FFs, so that, it reaches their reset inputs within one clock cycle.

Constraints:

General:

Please add constraints for meta stability to all '_meta' signals and timing ignore constraints to all '_async' signals.

Xilinx:

In case of a Xilinx device, this module will instantiate the optimized module xil_SyncReset. Please attend to the notes of xil_SyncReset.

Altera sdc file:

TODO

Generics

Name	Type	Default	Description
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Type	Direction	Description
Clock	std_logic	in	<Clock> output clock domain
Input	std_logic	in	@async: reset input
Output	std_logic	out	@Clock: reset output

×