[source]

Entity sortnet_Stream_Adapter

STREAM_DATA_BITSSTREAM_META_BITSSORTNET_IMPLSORTNET_SIZESORTNET_KEY_BITSSORTNET_DATA_BITSINVERSEClockstd_logicResetstd_logicIn_Validstd_logicIn_IsKeystd_logicIn_Data[STREAM_DATA_BITS - 1 downto 0]std_logic_vectorIn_Meta[STREAM_META_BITS - 1 downto 0]std_logic_vectorOut_Ackstd_logicIn_Ackstd_logicOut_Validstd_logicOut_IsKeystd_logicOut_Datastd_logic_vector[STREAM_DATA_BITS - 1 downto 0]Out_Metastd_logic_vector[STREAM_META_BITS - 1 downto 0]

Block Diagram of sortnet_Stream_Adapter

Generics

Name

Type

Default

Description

STREAM_DATA_BITS

positive

32

STREAM_META_BITS

positive

2

SORTNET_IMPL

T_SORTNET_IMPL

SORT_SORTNET_IMPL_ODDEVEN_MERGESORT

SORTNET_SIZE

positive

32

SORTNET_KEY_BITS

positive

32

SORTNET_DATA_BITS

natural

32

INVERSE

boolean

FALSE

Ports

Name

Type

Direction

Description

Clock

std_logic

in

Reset

std_logic

in

In_Valid

std_logic

in

In_IsKey

std_logic

in

In_Data

std_logic_vector

in

In_Meta

std_logic_vector

in

In_Ack

std_logic

out

Out_Valid

std_logic

out

Out_IsKey

std_logic

out

Out_Data

std_logic_vector

out

Out_Meta

std_logic_vector

out

Out_Ack

std_logic

in