Entity uart_fifo

Block Diagram of uart_fifo

Small FIFO s are included in this module, if larger or asynchronous transmit / receive FIFOs are required, then they must be connected externally.

old comments:

UART BAUD rate generator bclk = bit clock is rising bclk_x8 = bit clock times 8 is rising

Generics

Name	Type	Default	Description
CLOCK_FREQ	FREQ		Communication Parameters
BAUDRATE	BAUD
ADD_INPUT_SYNCHRONIZERS	boolean	TRUE
TX_MIN_DEPTH	positive	16	Buffer Dimensioning
TX_ESTATE_BITS	natural	0
RX_MIN_DEPTH	positive	16
RX_FSTATE_BITS	natural	0
FLOWCONTROL	T_IO_UART_FLOWCONTROL_KIND	UART_FLOWCONTROL_NONE	Flow Control
SWFC_XON_CHAR	std_logic_vector ( 7 downto 0 )	x"11"	^Q
SWFC_XON_TRIGGER	real	0.0625
SWFC_XOFF_CHAR	std_logic_vector ( 7 downto 0 )	x"13"	^S
SWFC_XOFF_TRIGGER	real	0.75

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
TX_put	std_logic	in	FIFO interface
TX_Data	std_logic_vector	in
TX_Full	std_logic	out
TX_EmptyState	std_logic_vector	out
RX_Valid	std_logic	out
RX_Data	std_logic_vector	out
RX_got	std_logic	in
RX_FullState	std_logic_vector	out
RX_Overflow	std_logic	out
UART_TX	std_logic	out	External pins
UART_RX	std_logic	in
UART_RTS	std_logic	out
UART_CTS	std_logic	in

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